ADMCF326BR Analog Devices Inc, ADMCF326BR Datasheet - Page 11

• Manufacturer Part Number: ADMCF326BR
• Description: IC DSP FLASH MOTOR CTRLR 28SOIC
• Manufacturer: Analog Devices Inc
• Series: Motor Controlr
• Type: Fixed Pointr

Specifications of ADMCF326BR

• Rohs Status: RoHS non-compliant
• Interface: Synchronous Serial Port (SSP)
• Clock Rate: 20MHz
• Non-volatile Memory: FLASH (12 kB), ROM (12kB)
• On-chip Ram: 2.5kB
• Voltage - I/o: 5.00V
• Voltage - Core: 5.00V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 28-SOIC (7.5mm Width)

The ADMCF326 reset sets all internal stack pointers to the
empty stack condition, masks all interrupts, clears the MSTAT
Register and performs a full reset of all of the motor control periph-
erals. Following a power-up, it is possible to initiate a DSP core
and motor control peripheral reset by pulling the RESET pin
low. The RESET signal must meet the minimum pulsewidth
specification, t
core starts executing code from the internal PM ROM located
at 0x0800.
DSP Control Registers
The DSP core has a system control register, SYSCNTL, memory
mapped at DM (0x3FFF). SPORT1 is configured as a serial
port when Bit 10 is set, or as flags and interrupt lines when this
bit is cleared. For proper operation of the ADMCF326, all other
bits in this register must be cleared.
The DSP core has a wait state control register, MEMWAIT,
memory mapped at DM (0x3FFE). The default value of this
resister is 0xFFFF. For proper operation of the ADMCF326,
this register must always contain the value 0x8000.
The configuration of both the SYSCNTL and MEMWAIT Reg-
isters of the ADMCF326 are shown at the end of the data sheet.
THREE-PHASE PWM CONTROLLER
Overview
The PWM generator block of the ADMCF326 is a flexible,
programmable, three-phase PWM waveform generator that can
be programmed to generate the required switching patterns to
drive a three-phase voltage source inverter for ac induction
motors (ACIM) or permanent magnet synchronous motors
(PMSM). In addition, the PWM block contains special functions
that considerably simplify the generation of the required PWM
switching patterns for control of electronically commutated motors
(ECM) or brushless dc motors (BDCM).
The PWM generator produces three pairs of active high PWM
signals on the six PWM output pins (AH, AL, BH, BL, CH, and
CL). The six PWM output signals consist of three high side
drive signals (AH, BH, and CH) and three low side drive signals
(AL, BL, and CL). The switching frequency, dead time, and
minimum pulsewidths of the generated PWM patterns are
programmable using, respectively, the PWMTM, PWMDT, and
PWMPD Registers. In addition, three registers (PWMCHA,
PWMCHB, and PWMCHC) control the duty cycles of the three
pairs of PWM signals.
Each of the six PWM output signals can be enabled or disabled
by separate output enable bits of the PWMSEG Register. In
REV. B
RESET
V
V
RST
DD
Figure 5. Power-On Reset Operation
RSP
. Following the reset sequence, the DSP
t
RST
V
RST –
V
HYST
–11–
addition, three control bits of the PWMSEG register permit
crossover of the two signals of a PWM pair for easy control of
ECM or BDCM. In crossover mode, the PWM signal destined
for the high side switch is diverted to the complementary low
side output, and the signal destined for the low side switch is
diverted to the corresponding high side output signal.
In many applications, there is a need to provide an isolation barrier
in the gate-drive circuits that turn on the power devices of the
inverter. In general, there are two common isolation techniques:
optical isolation using optocouplers, and transformer isolation
using pulse transformers. The PWM controller of the ADMCF326
permits mixing of the output PWM signals with a high frequency
chopping signal to permit an easy interface to such pulse trans-
formers. The features of this gate-drive chopping mode can be
controlled by the PWMGATE Register. There is an 8-bit value
within the PWMGATE Register that directly controls the chopping
frequency. In addition, high frequency chopping can be indepen-
dently enabled for the high side and the low side outputs using
separate control bits in the PWMGATE Register.
The PWM generator is capable of operating in two distinct modes:
Single Update Mode or Double Update Mode. In Single Update
mode, the duty cycle values are programmable only once per
PWM period, so that the resultant PWM patterns are symmetri-
cal about the midpoint of the PWM period. In the Double Update
Mode, a second updating of the PWM duty cycle values is imple-
mented at the midpoint of the PWM period. In this mode, it is
possible to produce asymmetrical PWM patterns that produce
lower harmonic distortion in three-phase PWM inverters. This
technique also permits the closed-loop controller to change the
average voltage applied to the machine winding at a faster rate,
allowing wider closed-loop bandwidths to be achieved. The operat-
ing mode of the PWM block (Single or Double Update Mode)
is selected by a control bit in MODECTRL Register.
The PWM generator of the ADMCF326 also provides an internal
signal that synchronizes the PWM switching frequency to the
A/D operation. In Single Update Mode, a PWMSYNC pulse is
produced at the start of each PWM period. In Double Update
Mode, an additional PWMSYNC pulse is produced at the mid-
point of each PWM period. The width of the PWMSYNC pulse
is programmable through the PWMSYNCWT Register.
The PWM signals produced by the ADMCF326 can be shut
off in a number of different ways. First, there is a dedicated
asynchronous PWM shutdown pin, PWMTRIP, which, when
brought LO, instantaneously places all six PWM outputs in
the LO state. Because this hardware shutdown mechanism is
asynchronous, and the associated PWM disable circuitry does
not use clocked logic, the PWM will shut down even if the DSP
clock is not running. The PWM system may also be shut down
from software by writing to the PWMSWT Register.
Status information about the PWM system of the ADMCF326
is available to the user in the SYSSTAT Register. In particular,
the state of PWMTRIP is available, as well as a status bit that
indicates whether operation is in the first half or the second half
of the PWM period.
ADMCF326