ADSP-2195MBCA-140 Analog Devices Inc, ADSP-2195MBCA-140 Datasheet - Page 15

• Manufacturer Part Number: ADSP-2195MBCA-140
• Description: IC DSP CONTROLLER 16BIT 144MBGA
• Manufacturer: Analog Devices Inc
• Series: ADSP-21xxr
• Type: Fixed Pointr

Specifications of ADSP-2195MBCA-140

• Rohs Status: RoHS non-compliant
• Interface: Host Interface, SPI, SSP, UART
• Clock Rate: 140MHz
• Non-volatile Memory: ROM (48 kB)
• On-chip Ram: 80kB
• Voltage - I/o: 3.30V
• Voltage - Core: 2.50V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 144-MBGA, 144-Mini-BGA

As indicated in
acting as a boot mode select during reset and determining
SPORT or SPI operation at runtime. If the OPMODE pin
at reset is the opposite of what is needed in an application
during runtime, the application needs to set the OPMODE
bit appropriately during runtime prior to using the corre-
sponding peripheral.
Booting Modes
The ADSP-2195 has seven mechanisms (listed in
for automatically loading internal program memory
after reset.
Table 6. Select Boot Mode (OPMODE, BMODE1, and
BMODE0)
The OPMODE, BMODE1, and BMODE0 pins, sampled
during hardware reset, and three bits in the Reset Configu-
ration Register implement these modes:
• Execute from memory external 16 bits—The memory
• Boot from EPROM—The EPROM boot routine located
• Boot from Host—The (8- or 16-bit) Host downloads a
REV. PrA
September 2001
0
0
0
0
1
1
1
1
boot routine located in boot ROM memory space
executes a boot-stream-formatted program located at
address 0x10000 of boot memory space, packing 16-bit
external data into 24-bit internal data. The External Port
Interface is configured for the default clock multiplier
(128) and read waitstates (7).
in boot ROM memory space executes a boot-stream-for-
matted program located at address 0x00000 of boot
memory space, packing 8- or 16-bit external data into
24-bit internal data. The External Port Interface is con-
figured for the default clock multiplier (32) and read
waitstates (7).
boot-stream-formatted program to internal or external
memory. The Host’s boot routine is located in internal
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Table
This information applies to a product under development. Its characteristics and specifications are subject to change with-
out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
Function
Execute from external memory 16 bits
(No Boot)
Boot from EPROM
Boot from Host
Reserved
Execute from external memory 8 bits
(No Boot)
Boot from UART
Boot from SPI, up to 4K bits
Boot from SPI, >4K bits up to
512K bits
6, the OPMODE pin has a dual role,
For current information contact Analog Devices at 800/262-5643
Table
6)
• Execute from memory external 8 bits (No Boot)—
• Boot from UART—The Host downloads
• Boot from SPI, up to 4K bits—The SPI0 port uses the
• Boot from SPI, from >4K bits to 512K bits—The SPI0
ROM memory space and uses the top 16 locations of
Page 0 program memory and the top 272 locations of
Page 0 data memory.
The internal boot ROM sets semaphore A (an IO register
within the host port) and then polls until the semaphore
is reset. Once detected, the internal boot ROM will remap
the interrupt vector table to Page 0 internal memory and
jump to address 0x0000 internal. From the point of view
of the host interface, an external host has full control of
the DSP's memory map. The Host has the freedom to
directly write internal memory, external memory, and
internal I/O memory space. The DSP core execution is
held off until the Host clears the semaphore register. This
strategy allows the maximum flexibility for the Host to
boot in the program and data code, by leaving it up to
the programmer.
execution starts from Page 1 of external memory space,
packing either 8- or 16-bit external data into 24-bit
internal data. The External Port Interface is configured
for the default clock multiplier (128) and read waitstates
(7).
boot-stream-formatted program using an autobaud
handshake sequence. The Host agent selects a baud rate
within the UART’s clocking capabilities. After a hardware
reset, the DSP’s UART transmits 0xFF values (eight bits
data, one start bit, one stop bit, no parity bit) until
detecting the start of the first memory block. The UART
boot routine is located in internal ROM memory space
and uses the top 16 locations of Page 0 program memory
and the top 272 locations of Page 0 data memory.
SPI0SEL1 (reconfigured PF2) output pin to select a
single serial EPROM device, submits a read command at
address 0x00, and begins clocking consecutive data into
internal or external memory. Use only SPI-compatible
EPROMs of 4K bit (12-bit address range). The SPI0
boot routine located in internal ROM memory space
executes a boot-stream-formatted program, using the top
16 locations of Page 0 program memory and the top 272
locations of Page 0 data memory. The SPI boot configu-
ration is SPIBAUD0=60 (decimal), CPHA=1, CPOL=1,
8-bit data, and MSB first.
port uses the SPI0SEL1 (re-configured PF2) output pin
to select a single serial EPROM device, submits a read
command at address 0x00, and begins clocking consecu-
tive data into internal or external memory. Use only
SPI-compatible EPROMs of
range). The SPI0 boot routine located in internal ROM
memory space executes a boot-stream-formatted
program, using the top 16 locations of Page 0 program
memory and the top 272 locations of Page 0 data memory.
4K bit (16-bit address
ADSP-2195
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