EP1C6T144C8 Altera, EP1C6T144C8 Datasheet - Page 31
![IC CYCLONE FPGA 5980 LE 144-TQFP](/photos/6/70/67061/544-144-tqfp_sml.jpg)
EP1C6T144C8
Manufacturer Part Number
EP1C6T144C8
Description
IC CYCLONE FPGA 5980 LE 144-TQFP
Manufacturer
Altera
Series
Cyclone®r
Datasheet
1.EP1C3T144C8.pdf
(106 pages)
Specifications of EP1C6T144C8
Number Of Logic Elements/cells
5980
Number Of Labs/clbs
598
Total Ram Bits
92160
Number Of I /o
98
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
144-TQFP, 144-VQFP
Family Name
Cyclone®
Number Of Logic Blocks/elements
5980
# I/os (max)
98
Frequency (max)
275.03MHz
Process Technology
0.13um (CMOS)
Operating Supply Voltage (typ)
1.5V
Logic Cells
5980
Ram Bits
92160
Operating Supply Voltage (min)
1.425V
Operating Supply Voltage (max)
1.575V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
144
Package Type
TQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Not Compliant
Other names
544-1058
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1C6T144C8
Manufacturer:
ALTERA
Quantity:
7
Company:
Part Number:
EP1C6T144C8
Manufacturer:
ALTERA
Quantity:
85
Company:
Part Number:
EP1C6T144C8N
Manufacturer:
RAIO
Quantity:
5 600
Company:
Part Number:
EP1C6T144C8N
Manufacturer:
ALTERA
Quantity:
586
Part Number:
EP1C6T144C8N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Part Number:
EP1C6T144C8NNY
Manufacturer:
ALTERA
Quantity:
20 000
Figure 2–17. Independent Clock Mode
Notes to
(1)
(2)
Altera Corporation
May 2008
clken
clock
wren
A
A
A
data
byteena
address
All registers shown have asynchronous clear ports.
Violating the setup or hold time on the address registers could corrupt the memory contents. This applies to both
read and write operations.
A
[ ]
6
A
Figure
A
[ ]
[ ]
6 LAB Row Clocks
2–17:
D
ENA
D
ENA
D
ENA
D
ENA
Q
Q
Q
Q
Independent Clock Mode
The M4K memory blocks implement independent clock mode for true
dual-port memory. In this mode, a separate clock is available for each port
(ports A and B). Clock A controls all registers on the port A side, while
clock B controls all registers on the port B side. Each port, A and B, also
supports independent clock enables and asynchronous clear signals for
port A and B registers.
independent clock mode.
Input/Output Clock Mode
Input/output clock mode can be implemented for both the true and
simple dual-port memory modes. On each of the two ports, A or B, one
clock controls all registers for inputs into the memory block: data input,
wren, and address. The other clock controls the block's data output
registers. Each memory block port, A or B, also supports independent
clock enables and asynchronous clear signals for input and output
registers.
clock mode.
Generator
Write
Pulse
Figures 2–18
D
ENA
Notes
Data In
Byte Enable A
Address A
Write/Read
Enable
Data Out
Q
A
(1),
Memory Block
256 ´ 16 (2)
q
1,024 ´ 4
2,048 ´ 2
4,096 ´ 1
A
512 ´ 8
[ ]
(2)
and
q
Figure 2–17
B
[ ]
Byte Enable B
Write/Read
Address B
2–19
Data Out
Data In
Enable
B
Q
ENA
show the memory block in input/output
D
shows an M4K memory block in
Generator
Write
Pulse
Q
Q
Q
Q
ENA
ENA
ENA
ENA
D
D
D
D
Embedded Memory
Preliminary
6
data
byteena
address
wren
clken
clock
2–25
B
B
B
B
[ ]
B
B
[ ]
[ ]