EP20K100QC240-3 Altera, EP20K100QC240-3 Datasheet - Page 42
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EP20K100QC240-3
Manufacturer Part Number
EP20K100QC240-3
Description
IC APEX 20K FPGA 100K 240-PQFP
Manufacturer
Altera
Series
APEX-20K®r
Datasheet
1.EP20K30ETC144-3.pdf
(117 pages)
Specifications of EP20K100QC240-3
Number Of Logic Elements/cells
4160
Number Of Labs/clbs
416
Total Ram Bits
53248
Number Of I /o
189
Number Of Gates
263000
Voltage - Supply
2.375 V ~ 2.625 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
240-MQFP, 240-PQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
544-1094
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP20K100QC240-3N
Manufacturer:
ALTERA
Quantity:
150
Part Number:
EP20K100QC240-3V
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
APEX 20K Programmable Logic Device Family Data Sheet
42
Each IOE drives a row, column, MegaLAB, or local interconnect when
used as an input or bidirectional pin. A row IOE can drive a local,
MegaLAB, row, and column interconnect; a column IOE can drive the
column interconnect.
interconnect.
Figure 27. Row IOE Connection to the Interconnect
Any LE can drive a
pin through the row,
column, and MegaLAB
interconnect.
Row Interconnect
LAB
An LE can drive a pin through the
local interconnect for faster
clock-to-output times.
Figure 27
shows how a row IOE connects to the
MegaLAB Interconnect
IOE
IOE
Each IOE can drive local,
MegaLAB, row, and column
interconnect. Each IOE data
and OE signal is driven by
the local interconnect.
Altera Corporation