EP20K100QC240-3 Altera, EP20K100QC240-3 Datasheet - Page 75
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EP20K100QC240-3
Manufacturer Part Number
EP20K100QC240-3
Description
IC APEX 20K FPGA 100K 240-PQFP
Manufacturer
Altera
Series
APEX-20K®r
Datasheet
1.EP20K30ETC144-3.pdf
(117 pages)
Specifications of EP20K100QC240-3
Number Of Logic Elements/cells
4160
Number Of Labs/clbs
416
Total Ram Bits
53248
Number Of I /o
189
Number Of Gates
263000
Voltage - Supply
2.375 V ~ 2.625 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
240-MQFP, 240-PQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
544-1094
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP20K100QC240-3N
Manufacturer:
ALTERA
Quantity:
150
Part Number:
EP20K100QC240-3V
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Altera Corporation
t
t
t
t
t
t
INSU
INH
OUTCO
INSUPLL
INHPLL
OUTCOPLL
Table 38. APEX 20KE External Timing Parameters
Symbol
Setup time with global clock at IOE input register
Hold time with global clock at IOE input register
Clock-to-output delay with global clock at IOE output register
Setup time with PLL clock at IOE input register
Hold time with PLL clock at IOE input register
Clock-to-output delay with PLL clock at IOE output register
Note to
(1)
Tables 38
t
t
t
TCH
TCL
TCLRP
TPREP
TESBCH
TESBCL
TESBWP
TESBRP
F1-4
F5-20
F20+
Table 36. APEX 20KE Routing Timing Microparameters
Table 37. APEX 20KE Functional Timing Microparameters
Symbol
Symbol
These parameters are worst-case values for typical applications. Post-compilation
timing simulation and timing analysis are required to determine actual worst-case
performance.
Table
and
36:
39
Fanout delay using Local Interconnect
Fanout delay estimate using MegaLab Interconnect
Fanout delay estimate using FastTrack Interconnect
Minimum clock high time from clock pin
Minimum clock low time from clock pin
LE clear Pulse Width
LE preset pulse width
Clock high time for ESB
Clock low time for ESB
Write pulse width
Read pulse width
Clock Parameter
describe the APEX 20KE external timing parameters.
APEX 20K Programmable Logic Device Family Data Sheet
Note (1)
Parameter
Parameter
Note (1)
C1 = 10 pF
C1 = 10 pF
Conditions
75