EPF81500AQC240-2 Altera, EPF81500AQC240-2 Datasheet - Page 26

• Manufacturer Part Number: EPF81500AQC240-2
• Description: IC FLEX 8000A FPGA 16K 240-PQFP
• Manufacturer: Altera
• Series: FLEX 8000r

Specifications of EPF81500AQC240-2

• Number Of Logic Elements/cells: 1296
• Number Of Labs/clbs: 162
• Number Of I /o: 181
• Number Of Gates: 16000
• Voltage - Supply: 4.75 V ~ 5.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 240-MQFP, 240-PQFP
• Family Name: FLEX 8000
• Number Of Usable Gates: 16000
• Number Of Logic Blocks/elements: 1296
• # Registers: 1500
• # I/os (max): 181
• Frequency (max): 125MHz
• Process Technology: CMOS
• Operating Supply Voltage (typ): 5V
• Logic Cells: 1296
• Ram Bits: 8
• Device System Gates: 16000
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: PQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Total Ram Bits: -
• Lead Free Status / Rohs Status: Not Compliant
• Other names: 544-2249

FLEX 8000 Programmable Logic Device Family Data Sheet
26
Generic Testing
f
For detailed information on JTAG operation in FLEX 8000 devices, refer to
Application Note 39 (IEEE 1149.1 (JTAG) Boundary-Scan Testing in Altera
Devices).
Each FLEX 8000 device is functionally tested and specified by Altera.
Complete testing of each configurable SRAM bit and all logic
functionality ensures 100% configuration yield. AC test measurements for
FLEX 8000 devices are made under conditions equivalent to those shown
in
during all stages of the production flow.
t
t
t
t
t
t
t
t
t
t
t
t
t
Symbol
JCP
JCH
JCL
JPSU
JPH
JPCO
JPZX
JPXZ
JSSU
JSH
JSCO
JSZX
JSXZ
Table 8. JTAG Timing Parameters & Values
Figure
TCK clock period
TCK clock high time
TCK clock low time
JTAG port setup time
JTAG port hold time
JTAG port clock to output
JTAG port high-impedance to valid output
JTAG port valid output to high-impedance
Capture register setup time
Capture register hold time
Update register clock to output
Update register high-impedance to valid output
Update register valid output to high-impedance
15. Designers can use multiple test patterns to configure devices
Parameter
Altera Corporation
EPF8282A
EPF8282AV
EPF8636A
EPF8820A
EPF81500A
Min
100
50
50
20
45
20
45
Max
25
25
25
35
35
35
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns