EP2C70F896C8N Altera, EP2C70F896C8N Datasheet - Page 42
![IC CYCLONE II FPGA 70K 896-FBGA](/photos/6/72/67288/544-cyclone_ii_896-fbga_sml.jpg)
EP2C70F896C8N
Manufacturer Part Number
EP2C70F896C8N
Description
IC CYCLONE II FPGA 70K 896-FBGA
Manufacturer
Altera
Series
Cyclone® IIr
Datasheet
1.EP2C5T144C8N.pdf
(168 pages)
Specifications of EP2C70F896C8N
Number Of Logic Elements/cells
68416
Number Of Labs/clbs
4276
Total Ram Bits
1152000
Number Of I /o
622
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
896-FBGA
For Use With
P0304 - DE2-70 CALL FOR ACADEMIC PRICING544-1703 - VIDEO KIT W/CYCLONE II EP2C70N544-1699 - DSP KIT W/CYCLONE II EPS2C70N
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Other names
544-1695
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP2C70F896C8N
Manufacturer:
ALTERA
Quantity:
513
Embedded Memory
2–30
Cyclone II Device Handbook, Volume 1
Memory Modes
Table 2–7
M4K memory blocks.
1
Single-port memory
Simple dual-port memory
Simple dual-port with mixed
width
True dual-port memory
True dual-port with mixed
width
Embedded shift register
ROM
FIFO buffers
Table 2–7. M4K Memory Modes
Memory Mode
Embedded Memory can be inferred in your HDL code or
directly instantiated in the Quartus II software using the
MegaWizard
summarizes the different memory modes supported by the
®
Plug-in Manager Memory Compiler feature.
M4K blocks support single-port mode, used when
simultaneous reads and writes are not required.
Single-port memory supports non-simultaneous
reads and writes.
Simple dual-port memory supports a
simultaneous read and write.
Simple dual-port memory mode with different
read and write port widths.
True dual-port mode supports any combination of
two-port operations: two reads, two writes, or one
read and one write at two different clock
frequencies.
True dual-port mode with different read and write
port widths.
M4K memory blocks are used to implement shift
registers. Data is written into each address
location at the falling edge of the clock and read
from the address at the rising edge of the clock.
The M4K memory blocks support ROM mode. A
MIF initializes the ROM contents of these blocks.
A single clock or dual clock FIFO may be
implemented in the M4K blocks. Simultaneous
read and write from an empty FIFO buffer is not
supported.
Description
Altera Corporation
February 2007