EP2S30F484C5 Altera, EP2S30F484C5 Datasheet - Page 187

• Manufacturer Part Number: EP2S30F484C5
• Description: IC STRATIX II FPGA 30K 484-FBGA
• Manufacturer: Altera
• Series: Stratix® IIr

Specifications of EP2S30F484C5

• Number Of Logic Elements/cells: 33880
• Number Of Labs/clbs: 1694
• Total Ram Bits: 1369728
• Number Of I /o: 342
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Other names: 544-1107

Altera Corporation
April 2011
Notes to
(1)
(2)
(3)
Input delay from
pin to internal
cells
Input delay from
pin to input
register
Delay from
output register
to output pin
Output enable
pin delay
Table 5–69. Stratix II IOE Programmable Delay on Column Pins
Parameter
The incremental values for the settings are generally linear. For the exact delay associated with each setting, use the
latest version of the Quartus II software.
The first number is the minimum timing parameter for industrial devices. The second number is the minimum
timing parameter for commercial devices.
The first number applies to -3 speed grade EP2S15, EP2S30, EP2S60, and EP2S90 devices. The second number
applies to -3 speed grade EP2S130 and EP2S180 devices.
Table
5–69:
Pad to I/O
dataout to logic
array
Pad to I/O input
register
I/O output
register to pad
t
Paths Affected
X Z
, t
Z X
IOE Programmable Delay
See
Tables 5–69
Available
Settings
64
8
2
2
Offset
and
Min
(ps)
Timing
Minimum
0
0
0
0
0
0
0
0
5–70
Offset
1,696
1,781
1,955
2,053
Max
(ps)
316
332
305
320
(2)
for IOE programmable delay.
Offset
(ps)
Min
Grade
-3 Speed
0
0
0
0
0
0
0
0
Note (1)
Stratix II Device Handbook, Volume 1
Offset
2,881
3,025
3,275
3,439
(3)
Max
(ps)
500
525
483
507
DC & Switching Characteristics
Offset
(ps)
Min
-4 Speed
0
0
0
0
Grade
Offset
3,313
3,766
Max
(ps)
575
556
Offset
(ps)
Min
0
0
0
0
-5 Speed
Grade
Offset
3,860
4,388
Max
(ps)
670
647
5–51