EP3C120F484C7N Altera, EP3C120F484C7N Datasheet - Page 13

• Manufacturer Part Number: EP3C120F484C7N
• Description: IC CYCLONE III FPGA 120K 484FBGA
• Manufacturer: Altera
• Series: Cyclone® IIIr

Specifications of EP3C120F484C7N

• Number Of Logic Elements/cells: 119088
• Number Of Labs/clbs: 7443
• Total Ram Bits: 3981312
• Number Of I /o: 283
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Cyclone III
• Number Of Logic Blocks/elements: 119088
• # I/os (max): 283
• Frequency (max): 437.5MHz
• Process Technology: 65nm
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 119088
• Ram Bits: 3981312
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FBGA
• For Use With: 544-2601 - KIT DEV CYCLONE III LS EP3CLS200544-2589 - KIT DEV EMB CYCLONE III EDITION544-2566 - KIT DEV DSP CYCLONE III EDITION544-2444 - KIT DEV CYCLONE III EP3C120544-2411 - KIT DEV NIOS II CYCLONE III ED.
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-2528

Revision History
© December 2009 Altera Corporation
This section provides a complete overview of all features relating to the Cyclone
device family, which is the most architecturally advanced, high-performance,
low-power FPGA in the market place. This section includes the following chapters:
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Refer to each chapter for its own specific revision history. For information about when
each chapter was updated, refer to the Chapter Revision Dates section, which appears
in the complete handbook.
Chapter 1, Cyclone III Device Family Overview
Chapter 2, Logic Elements and Logic Array Blocks in the Cyclone III Device
Family
Chapter 3, Memory Blocks in the Cyclone III Device Family
Chapter 4, Embedded Multipliers in the Cyclone III Device Family
Chapter 5, Clock Networks and PLLs in the Cyclone III Device Family
Section 1. Device Core
Cyclone III Device Handbook, Volume 1
®
III