EP2S60F484C5N Altera, EP2S60F484C5N Datasheet - Page 78

IC STRATIX II FPGA 60K 484-FBGA

EP2S60F484C5N

Manufacturer Part Number
EP2S60F484C5N
Description
IC STRATIX II FPGA 60K 484-FBGA
Manufacturer
Altera
Series
Stratix® IIr
Datasheet

Specifications of EP2S60F484C5N

Number Of Logic Elements/cells
60440
Number Of Labs/clbs
3022
Total Ram Bits
2544192
Number Of I /o
334
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
Family Name
Stratix II
Number Of Logic Blocks/elements
60440
# I/os (max)
334
Frequency (max)
609.76MHz
Process Technology
90nm (CMOS)
Operating Supply Voltage (typ)
1.2V
Logic Cells
60440
Ram Bits
2544192
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
484
Package Type
FC-FBGA
For Use With
544-1700 - DSP KIT W/STRATIX II EP2S60N544-1697 - NIOS II KIT W/STRATIX II EP2S60N
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-1908
EP2S60F484C5N

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP2S60F484C5N
Manufacturer:
ALTERA
Quantity:
238
Part Number:
EP2S60F484C5N
Manufacturer:
Altera
Quantity:
10 000
Part Number:
EP2S60F484C5N
Manufacturer:
ALTERA
0
Part Number:
EP2S60F484C5N
Manufacturer:
ALTERA
Quantity:
200
Part Number:
EP2S60F484C5N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Part Number:
EP2S60F484C5N
0
I/O Structure
2–70
Stratix II Device Handbook, Volume 1
The IOE in Stratix II devices contains a bidirectional I/O buffer, six
registers, and a latch for a complete embedded bidirectional single data
rate or DDR transfer.
IOE contains two input registers (plus a latch), two output registers, and
two output enable registers. The design can use both input registers and
the latch to capture DDR input and both output registers to drive DDR
outputs. Additionally, the design can use the output enable (OE) register
for fast clock-to-output enable timing. The negative edge-clocked OE
register is used for DDR SDRAM interfacing. The Quartus II software
automatically duplicates a single OE register that controls multiple
output or bidirectional pins.
Output drive strength control
Tri-state buffers
Bus-hold circuitry
Programmable pull-up resistors
Programmable input and output delays
Open-drain outputs
DQ and DQS I/O pins
Double data rate (DDR) registers
Figure 2–46
shows the Stratix II IOE structure. The
Altera Corporation
May 2007

Related parts for EP2S60F484C5N