XC3S500E-4FGG320C Xilinx Inc, XC3S500E-4FGG320C Datasheet - Page 105

• Manufacturer Part Number: XC3S500E-4FGG320C
• Description: IC SPARTAN-3E FPGA 500K 320FBGA
• Manufacturer: Xilinx Inc
• Series: Spartan™-3Er

Specifications of XC3S500E-4FGG320C

• Total Ram Bits: 368640
• Number Of Logic Elements/cells: 10476
• Number Of Labs/clbs: 1164
• Number Of I /o: 232
• Number Of Gates: 500000
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 320-BGA
• No. Of Logic Blocks: 10476
• No. Of Gates: 500000
• No. Of Macrocells: 10476
• No. Of Speed Grades: 4
• No. Of I/o's: 250
• Clock Management: DLL
• Package: 320FBGA
• Family Name: Spartan®-3E
• Device Logic Cells: 10476
• Device Logic Units: 1164
• Device System Gates: 500000
• Number Of Registers: 9312
• Maximum Internal Frequency: 572 MHz
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 232
• Ram Bits: 368640
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 122-1536 - KIT STARTER SPARTAN-3E
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 122-1526

DS312-2 (v3.8) August 26, 2009
Product Specification
R
No
No
and V
Figure 67: General Configuration Process
Sample mode pins
Clear configuration
Load configuration
and V
INIT_ B = High?
Reconfigure?
data frames
V
Yes
User mode
Power-On
CCO
Yes
sequence
Yes
CCINT
Start-Up
correct?
memory
CCAUX
CRC
Bank 2 > 1V
>1V
> 2V
www.xilinx.com
Yes
DONE pin goes High,
signaling end of
configuration
No
M[2:0] and VS[2:0]
pins are sampled on
INIT_B rising edge
No
Yes
Set PROG_B Low
after Power-On
PROG_B = Low
INIT_B goes Low.
Abort Start-Up
No
DS312-2_58_051706
Functional Description
105