XC3S1400AN-4FGG676C Xilinx Inc, XC3S1400AN-4FGG676C Datasheet - Page 21
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XC3S1400AN-4FGG676C
Manufacturer Part Number
XC3S1400AN-4FGG676C
Description
IC SPARTAN-3AN FPGA 1400K 676FBG
Manufacturer
Xilinx Inc
Series
Spartan™-3ANr
Datasheets
1.XC3S50A-4VQG100C.pdf
(7 pages)
2.XC3S50AN-4TQG144C.pdf
(2 pages)
3.XC3S50AN-4TQG144C.pdf
(123 pages)
Specifications of XC3S1400AN-4FGG676C
Total Ram Bits
589824
Number Of Logic Elements/cells
25344
Number Of Labs/clbs
2816
Number Of I /o
502
Number Of Gates
1400000
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
676-BBGA
No. Of Logic Blocks
25344
No. Of Gates
1400000
No. Of Macrocells
25344
Family Type
Spartan-3AN
No. Of Speed Grades
4
No. Of I/o's
502
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
122-1552
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC3S1400AN-4FGG676C
Manufacturer:
XILINX
Quantity:
201
Company:
Part Number:
XC3S1400AN-4FGG676C
Manufacturer:
Xilinx Inc
Quantity:
10 000
Part Number:
XC3S1400AN-4FGG676C
Manufacturer:
XILINX/赛灵思
Quantity:
20 000
Table 16: DC Characteristics of User I/Os Using Differential Signal Standards
DS557 (v4.1) April 1, 2011
Product Specification
Notes:
1.
2.
3.
4.
LVDS_25
LVDS_33
BLVDS_25
MINI_LVDS_25
MINI_LVDS_33
RSDS_25
RSDS_33
TMDS_33
PPDS_25
PPDS_33
DIFF_HSTL_I_18
DIFF_HSTL_II_18
DIFF_HSTL_III_18
DIFF_HSTL_I
DIFF_HSTL_III
DIFF_SSTL18_I
DIFF_SSTL18_II
DIFF_SSTL2_I
DIFF_SSTL2_II
DIFF_SSTL3_I
DIFF_SSTL3_II
IOSTANDARD Attribute
The numbers in this table are based on the conditions set forth in
See
Output voltage measurements for all differential standards are made with a termination resistor (R
differential signal pair.
At any given time, no more than two of the following differential output standards can be assigned to an I/O bank: LVDS_25, RSDS_25,
MINI_LVDS_25, PPDS_25 when V
External Termination Requirements for Differential I/O, page
Min (mV)
247
247
240
300
300
100
100
400
100
100
–
–
–
–
–
–
–
–
–
–
–
CCO
Typ (mV)
=2.5V, or LVDS_33, RSDS_33, MINI_LVDS_33, TMDS_33, PPDS_33 when V
V
350
350
350
OD
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Max (mV)
454
454
460
600
600
400
400
800
400
400
–
–
–
–
–
–
–
–
–
–
–
www.xilinx.com
Spartan-3AN FPGA Family: DC and Switching Characteristics
V
CCO
22.
Table 10
Min (V)
1.125
1.125
1.0
1.0
1.0
1.0
0.5
0.5
– 0.405
–
–
–
–
–
–
–
–
–
–
–
–
and
Table
Typ (V)
V
1.30
0.8
0.8
OCM
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
15.
V
CCO
Max (V)
1.375
1.375
T
1.4
1.4
1.4
1.4
1.4
1.4
) of 100 across the N and P pins of the
– 0.190
–
–
–
–
–
–
–
–
–
–
–
–
V
V
V
V
V
V
V
V
V
V
V
TT
TT
CCO
CCO
CCO
CCO
CCO
Min (V)
TT
TT
TT
TT
V
+ 0.475
+ 0.475
+ 0.61
+ 0.81
OH
–
–
–
–
–
–
–
–
–
–
+ 0.6
+ 0.8
– 0.4
– 0.4
– 0.4
– 0.4
– 0.4
CCO
= 3.3V
V
V
V
V
V
V
TT
TT
Max (V)
TT
TT
TT
TT
V
0.4
0.4
0.4
0.4
0.4
– 0.475
– 0.475
– 0.61
– 0.81
OL
–
–
–
–
–
–
–
–
–
–
– 0.6
– 0.8
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