EP3C80F780C7 Altera, EP3C80F780C7 Datasheet - Page 71
![IC CYCLONE III FPGA 80K 780FBGA](/photos/6/72/67270/544-780-fbga_sml.jpg)
EP3C80F780C7
Manufacturer Part Number
EP3C80F780C7
Description
IC CYCLONE III FPGA 80K 780FBGA
Manufacturer
Altera
Series
Cyclone® IIIr
Datasheets
1.EP3C5F256C8N.pdf
(5 pages)
2.EP3C5F256C8N.pdf
(34 pages)
3.EP3C5F256C8N.pdf
(66 pages)
4.EP3C5F256C8N.pdf
(14 pages)
5.EP3C5F256C8N.pdf
(76 pages)
Specifications of EP3C80F780C7
Number Of Logic Elements/cells
81264
Number Of Labs/clbs
5079
Total Ram Bits
2810880
Number Of I /o
429
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
780-FBGA
For Use With
544-2601 - KIT DEV CYCLONE III LS EP3CLS200544-2411 - KIT DEV NIOS II CYCLONE III ED.
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Other names
544-2521
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP3C80F780C7N
Manufacturer:
ALTERA
Quantity:
1 364
Chapter 2: Cyclone III LS Device Data Sheet
Glossary
Table 2–39. Glossary (Part 2 of 5)
© December 2009
Letter
Q
R
P
PLL Block
R
Receiver Input
Waveform
RSKM (Receiver
input skew
margin)
L
Term
—
Altera Corporation
The following block diagram highlights the PLL specification parameters.
Receiver differential input discrete resistor (external to the Cyclone III LS device)
Receiver Input Waveform for LVDS and LVPECL Differential Standards
High-speed I/O Block: The total margin left after accounting for the sampling window and
TCCS. RSKM = (TUI – SW – TCCS) / 2
Core Clock
Key
Single-Ended Waveform
Differential Input Waveform
CLK
Reconfigurable in User Mode
V
CM
Switchover
V
f
ID
IN
N
f
INPFD
V
ID
Definitions
PFD
—
M
CP
Phase tap
LF
VCO
Cyclone III Device Handbook, Volume 2
f
VCO
V
p - n
Positive Channel (p) = V
Negative Channel (n) = V
Ground
ID
0 V
Counters
C0..C4
CLKOUT Pins
f
f
OUT _EXT
OUT
GCLK
IH
IL
2–27