EP2S90F1020I4N Altera, EP2S90F1020I4N Datasheet - Page 163
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EP2S90F1020I4N
Manufacturer Part Number
EP2S90F1020I4N
Description
IC STRATIX II FPGA 90K 1020-FBGA
Manufacturer
Altera
Series
Stratix® IIr
Datasheet
1.EP2S15F484I4N.pdf
(238 pages)
Specifications of EP2S90F1020I4N
Number Of Logic Elements/cells
90960
Number Of Labs/clbs
4548
Total Ram Bits
4520488
Number Of I /o
758
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
1020-FBGA
Family Name
Stratix II
Number Of Logic Blocks/elements
90960
# I/os (max)
758
Frequency (max)
711.24MHz
Process Technology
90nm (CMOS)
Operating Supply Voltage (typ)
1.2V
Logic Cells
90960
Ram Bits
4520488
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
1020
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-1920
EP2S90F1020I4N
EP2S90F1020I4N
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP2S90F1020I4N
Manufacturer:
ALTERA
Quantity:
450
Company:
Part Number:
EP2S90F1020I4N
Manufacturer:
ALTERA
Quantity:
531
Part Number:
EP2S90F1020I4N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Altera Corporation
April 2011
Notes to
(1)
(2)
(3)
(4)
(5)
(6)
1.8-V HSTL Class II
1.5-V HSTL Class I
1.5-V HSTL Class II
1.2-V HSTL with OCT
Differential SSTL-2 Class I
Differential SSTL-2 Class II
Differential SSTL-18 Class I
Differential SSTL-18 Class II
1.5-V Differential HSTL Class I
1.5-V Differential HSTL Class II
1.8-V Differential HSTL Class I
1.8-V Differential HSTL Class II
LVDS
HyperTransport
LVPECL
Table 5–35. Timing Measurement Methodology for Input Pins (Part 2 of 2)
Input buffer sees no load at buffer input.
Input measuring point at buffer input is 0.5 × V
Output measuring point is 0.5 × V
Input edge rate is 1 V/ns.
Less than 50-mV ripple on V
V
CCPD
Table
= 2.97 V, less than 50-mV ripple on V
I/O Standard
5–35:
Performance
Table 5–36
performance values were obtained with the Quartus II software
compilation of library of parameterized modules (LPM), or MegaCore
functions for the finite impulse response (FIR) and fast Fourier transform
(FFT) designs.
CCIO
and V
CC
at internal node.
CCPD
shows Stratix II performance for some common designs. All
V
CCIO
, V
CCIO
1.660
1.375
1.375
1.140
2.325
2.325
1.660
1.660
1.375
1.375
1.660
1.660
2.325
2.325
3.135
CCINT
CCIO
and V
(V)
Measurement Conditions
.
= 1.15 V with less than 30-mV ripple
CCPD
, V
V
0.830
0.688
0.688
0.570
1.163
1.163
0.830
0.830
0.688
0.688
0.830
0.830
REF
CCINT
(V)
= 1.15 V
Stratix II Device Handbook, Volume 1
Edge Rate (ns)
DC & Switching Characteristics
1.660
1.375
1.375
1.140
2.325
2.325
1.660
1.660
1.375
1.375
1.660
1.660
0.100
0.400
0.100
Notes (1)–(4)
Measurement Point
V
M E A S
0.6875
0.6875
0.6875
0.6875
1.1625
1.1625
1.5675
1.1625
1.1625
0.570
0.83
0.83
0.83
0.83
0.83
(V)
5–27
®