EP2S90F1020I4N Altera, EP2S90F1020I4N Datasheet - Page 76
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EP2S90F1020I4N
Manufacturer Part Number
EP2S90F1020I4N
Description
IC STRATIX II FPGA 90K 1020-FBGA
Manufacturer
Altera
Series
Stratix® IIr
Datasheet
1.EP2S15F484I4N.pdf
(238 pages)
Specifications of EP2S90F1020I4N
Number Of Logic Elements/cells
90960
Number Of Labs/clbs
4548
Total Ram Bits
4520488
Number Of I /o
758
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
1020-FBGA
Family Name
Stratix II
Number Of Logic Blocks/elements
90960
# I/os (max)
758
Frequency (max)
711.24MHz
Process Technology
90nm (CMOS)
Operating Supply Voltage (typ)
1.2V
Logic Cells
90960
Ram Bits
4520488
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
1020
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-1920
EP2S90F1020I4N
EP2S90F1020I4N
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP2S90F1020I4N
Manufacturer:
ALTERA
Quantity:
450
Company:
Part Number:
EP2S90F1020I4N
Manufacturer:
ALTERA
Quantity:
531
Part Number:
EP2S90F1020I4N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
PLLs & Clock Networks
Figure 2–44. Stratix II Enhanced PLL
Notes to
(1)
(2)
(3)
(4)
2–68
Stratix II Device Handbook, Volume 1
Global or
Regional
Clock
INCLK[3..0]
Each clock source can come from any of the four clock pins that are physically located on the same side of the device
as the PLL.
If the feedback input is used, you lose one (or two, if FBIN is differential) external clock output pin.
Each enhanced PLL has three differential external clock outputs or six single-ended external clock outputs.
The global or regional clock input can be driven by an output from another PLL, a pin-driven dedicated global or
regional clock, or through a clock control block, provided the clock control block is fed by an output from another
PLL or a pin-driven dedicated global or regional clock. An internally generated global signal cannot drive the PLL.
(4)
Figure
4
Shaded Portions of the
PLL are Reconfigurable
2–44:
FBIN
Switchover
Circuitry
Clock
(2)
Enhanced PLLs
Stratix II devices contain up to four enhanced PLLs with advanced clock
management features.
/n
Phase Frequency
Detector
PFD
Note (1)
Charge
Pump
Lock Detect
& Filter
Spectrum
Spread
/m
Filter
Loop
VCO Phase Selection
Affecting All Outputs
VCO Phase Selection
Selectable at Each
PLL Output Port
Figure 2–44
VCO
8
shows a diagram of the enhanced PLL.
Post-Scale
Counters
/c0
/c1
/c2
/c3
/c4
/c5
From Adjacent PLL
6
Altera Corporation
4
8
6
Global
Clocks
Regional
Clocks
I/O Buffers (3)
to I/O or general
routing
May 2007