XC4005L-5PQ208C Xilinx Inc, XC4005L-5PQ208C Datasheet - Page 67
XC4005L-5PQ208C
Manufacturer Part Number
XC4005L-5PQ208C
Description
IC 3.3V FPGA 196 CLB'S 208-PQFP
Manufacturer
Xilinx Inc
Series
XC4000r
Datasheet
1.XC4005L-5PC84C.pdf
(175 pages)
Specifications of XC4005L-5PQ208C
Number Of Logic Elements/cells
466
Number Of Labs/clbs
196
Total Ram Bits
6272
Number Of I /o
112
Number Of Gates
5000
Voltage - Supply
3 V ~ 3.6 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
208-BFQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
122-1122
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Notes: 1. At power-up, Vcc must rise from 2.0 V to Vcc min in less than 25 ms, otherwise delay configuration by pulling PROGRAM
This timing diagram shows that the EPROM requirements are extremely relaxed. EPROM access time can be longer than
500 ns. EPROM data output has no hold-time requirements.
Figure 58: Master Parallel Mode Programming Switching Characteristics
September 18, 1996 (Version 1.04)
(output)
(output)
(output)
(output)
A0-A17
D0-D7
DOUT
RCLK
CCLK
RCLK
2. The first Data byte is loaded and CCLK starts at the end of the first RCLK active cycle (rising edge).
Low until Vcc is valid.
Delay to Address valid
Data setup time
Data hold time
Description
Address for Byte n
1
2
3
Symbol
7 CCLKs
T
T
T
RAC
DRC
RCD
2 T
Byte
DRC
Min
60
0
0
Byte n - 1
D6
Address for Byte n + 1
1 T
3 T
CCLK
RAC
RCD
Max
200
D7
Units
ns
ns
ns
X6078
4-71
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