XC4005L-5PQ100C Xilinx Inc, XC4005L-5PQ100C Datasheet
XC4005L-5PQ100C
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XC4005L-5PQ100C Summary of contents
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September 18, 1996 (Version 1.04) XC4000-Series Features Note: XC4000-Series devices described in this data sheet include the XC4000E, XC4000EX, XC4000XL. This information does not apply to the older Xilinx families: XC4000, XC4000A, XC4000D or XC4000H. For information on these devices, ...
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XC4000 Series Field Programmable Gate Arrays Table 1: XC4000-Series Field Programmable Gate Arrays Max Logic Max. RAM Gates Device (No RAM) (No Logic) XC4003E 3,000 3,200 XC4005E/L 5,000 6,272 XC4006E 6,000 8,192 XC4008E 8,000 10,368 XC4010E/L 10,000 12,800 XC4013E/L 13,000 ...
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Table 2: Density and Performance for Several Common Circuit Functions in XC4000E Design Class Function 256 x 8 Single Port (read/modify/write bit FIFO Memory simultaneous read/write MUXed read/write 9 bit Shift Register (with enable) 16 bit Pre-Scaled ...
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XC4000 Series Field Programmable Gate Arrays XC4000E and XC4000EX Families Compared to the XC4000 For readers already familiar with the XC4000 family of Xil- inx Field Programmable Gate Arrays, the major new fea- tures in the XC4000-Series devices are listed ...
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Global Signal Access to Logic There is additional access from global clocks to the F and G function generator inputs. Configuration Pin Pull-Up Resistors During configuration, the three mode pins, M0, M1, and M2, have weak pull-up resistors. For the ...
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XC4000 Series Field Programmable Gate Arrays Table 3: CLB Count of Selected XC4000-Series Soft Macros 7400 Equivalents CLBs Barrel Shifters ‘138 5 ‘139 2 ‘147 5 ‘148 6 ‘150 5 ‘151 3 ‘152 3 ‘153 2 ‘154 16 ‘157 2 ...
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Detailed Functional Description XC4000-Series devices achieve high speed through advanced semiconductor technology and improved archi- tecture. The XC4000E and XC4000EX support system clock rates MHz and internal performance in excess of 150 MHz. Compared to older ...
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XC4000 Series Field Programmable Gate Arrays • • • LOGIC FUNCTION G1- LOGIC FUNCTION F1- ...
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Clock Enable The clock enable signal (EC) is active High. The EC pin is shared by both storage elements. If left unconnected for either, the clock enable for that storage element defaults to the active state not invertible ...
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XC4000 Series Field Programmable Gate Arrays Using Function Generators as RAM Optional modes for each CLB make the memory look-up tables in the F’ and G’ function generators usable as an array of Read/Write memory cells. Available modes are level-sensitive ...
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C 1 • • • • • • • • • (CLOCK) Figure 3: 16x2 (or 16x1) Edge-Triggered Single-Port RAM • • • ...
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XC4000 Series Field Programmable Gate Arrays RAM Inputs and Outputs The F1-F4 and G1-G4 inputs to the function generators act as address lines, selecting a particular memory cell in each look-up table. The functionality of the CLB control signals changes ...
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Dual-Port Edge-Triggered Mode In dual-port mode, both the F and G function generators are used to create a single 16x1 RAM array with one write port and two read ports. The resulting RAM array can be read and written simultaneously ...
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XC4000 Series Field Programmable Gate Arrays • • • • • • • • • (CLOCK) Figure 7: 16x1 Edge-Triggered Dual-Port ...
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Single-Port Level-Sensitive Timing Mode Note: Edge-triggered mode is recommended for all new designs. Level-sensitive mode, also called asynchronous mode, is still supported for XC4000-Series backward-com- patibility with the XC4000 family. Level-sensitive RAM timing is simple in concept but can be ...
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XC4000 Series Field Programmable Gate Arrays • • • • • • • • • X6746 Figure 9: 16x2 (or 16x1) Level-Sensitive Single-Port RAM 4 C ...
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Fast Carry Logic Each CLB F and G function generator contains dedicated arithmetic logic for the fast generation of carry and borrow signals. This extra output is passed on to the function gen- erator in the adjacent CLB. The carry ...
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XC4000 Series Field Programmable Gate Arrays C C OUT IN CARRY LOGIC G CARRY OUT0 H1 F CARRY Figure 13: Fast Carry Logic in XC4000E CLB (shaded area ...
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X2000 Figure 14: Detail of XC4000E Dedicated Carry Logic Figure 15: Detail of XC4000EX Dedicated Carry Logic (shaded areas show differences ...
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XC4000 Series Field Programmable Gate Arrays Input/Output Blocks (IOBs) User-configurable input/output blocks (IOBs) provide the interface between external package pins and the internal logic. Each IOB controls one package pin and can be con- figured for input, output, or bidirectional ...
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T Out Output Clock Clock Enable Input Clock Figure 16: Simplified Block Diagram of XC4000E IOB T Out Output Clock Clock Enable Input Clock Figure 17: Simplified Block Diagram of XC4000EX IOB ...
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XC4000 Series Field Programmable Gate Arrays Optional Delay Guarantees Zero Hold Time The data input to the register can optionally be delayed by several nanoseconds. With the delay enabled, the setup time of the input flip-flop is increased so that ...
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Since the FastCLK pads are different from the Global Early and Global Low-Skew pads, care must be taken to ensure that skew external to ...
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XC4000 Series Field Programmable Gate Arrays OPAD OBUFT X6702 Figure 19: Open-Drain Output An output can be configured as open-drain (open-collector) by placing an OBUFT symbol in a schematic or HDL code, then tying the 3-state pin (T) to the ...
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OAND2 S0 X6598 Figure 21: Output AND and MUX Symbols in XC4000EX IOB The user can specify that the IOB function generator be used, by placing special library symbols beginning with the letter “O.” For example, a ...
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XC4000 Series Field Programmable Gate Arrays The buffer enable is an active-High 3-state (i.e. an active- Low enable), as shown in Table 15. Another 3-state buffer with similar access is located near each I/O block along the right and left ...
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Wide Edge Decoders Dedicated decoder circuitry boosts the performance of wide decoding functions. When the address or data field is wider than the function generator inputs, FPGAs need multi-level decoding and are thus slower than PALs. XC4000-Series CLBs have nine ...
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XC4000 Series Field Programmable Gate Arrays Programmable Interconnect All internal connections are composed of metal segments with programmable switching points and switching matrices to implement the desired routing. A structured, hierarchical matrix of routing resources is provided to achieve efficient ...
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Quad Long Global Clock Figure 26: High-Level Routing Diagram of XC4000-Series CLB (shaded arrows indicate XC4000EX only) September 18, 1996 (Version 1.04) Long Double Single Global Clock Quad Single Double Long Direct CLB Connect Long Carry Direct Chain Connect x5994 ...
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XC4000 Series Field Programmable Gate Arrays Common to XC4000E and XC4000EX XC4000EX only Programmable Switch Matrix Figure 27: Detail of Programmable Interconnect Associated with XC4000-Series CLB 4-34 QUAD DOUBLE SINGLE DOUBLE LONG DIRECT ...
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Double Singles Double Figure 28: Programmable Switch Matrix (PSM) Programmable Switch Matrices The horizontal and vertical single- and double-length lines intersect at a box called a programmable switch matrix (PSM). Each switch matrix consists of programmable pass transistors used to ...
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XC4000 Series Field Programmable Gate Arrays Quad Lines (XC4000EX only) XC4000EX devices also include twelve vertical and twelve horizontal quad lines per CLB row and column. Quad lines are four times as long as the single-length lines. They are interconnected ...
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Longlines Longlines form a grid of metal interconnect segments that run the entire length or width of the array. Longlines are intended for high fan-out, time-critical signal nets, or nets that are distributed over long distances. In XC4000EX devices, quad ...
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XC4000 Series Field Programmable Gate Arrays I/O Routing XC4000-Series devices have additional routing around the IOB ring. This routing is called a VersaRing. VersaRing facilitates pin-swapping and redesign without affecting board layout. Included are eight double-length lines spanning two CLBs ...
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Common to XC4000E and XC4000EX XC4000EX only Figure 33: Detail of Programmable Interconnect Associated with XC4000-Series IOB (Left Edge) September 18, 1996 (Version 1.04) IOB IOB ...
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XC4000 Series Field Programmable Gate Arrays Octal I/O Routing (XC4000EX only) Between the XC4000EX CLB array and the pad ring, eight interconnect tracks provide for versatility in pin assignment and fixed pinout flexibility. (See Figure These routing tracks are called ...
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Global Nets and Buffers Both the XC4000E and the XC4000EX have dedicated glo- bal networks. These networks are designed to distribute clocks and other high fanout control signals throughout the devices with minimal skew. The global buffers are described in ...
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XC4000 Series Field Programmable Gate Arrays BUFGS PGCK1 SGCK1 BUFGP 4 IOB locals Any BUFGS X4 locals One BUFGP per Global Line IOB BUFGS PGCK2 SGCK2 BUFGP Figure 35: XC4000E Global Net Distribution BUFGLS GCK1 GCK8 BUFGE BUFGLS BUFGE BUFFCLK ...
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Global Nets and Buffers (XC4000EX only) Eight vertical longlines in each CLB column are driven by special global buffers. These longlines are in addition to the vertical longlines used for standard interconnect. The global lines are broken in the center ...
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XC4000 Series Field Programmable Gate Arrays 8 IOB 1 I CLB CLB IOB 3 Figure 37: Any BUFGLS (GCK1 - GCK8) Can Drive Any or All Clock Inputs on the Device Global Early Buffers ...
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The Global Early buffers can be driven by either semi-ded- icated pads or internal logic. They share pads with the Glo- bal Low-Skew buffers single net can drive both global buffers, as described above. To use a Global ...
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XC4000 Series Field Programmable Gate Arrays Power Distribution Power for the FPGA is distributed through a grid to achieve high noise immunity and isolation between logic and I/O. Inside the FPGA, a dedicated Vcc and Ground ring sur- rounding the ...
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Table 18: Pin Descriptions I/O I/O During After Pin Name Config. Config. Permanently Dedicated Pins Eight or more (depending on package) connections to the nominal +5 V supply voltage VCC I I (+3.3 V for low-voltage devices). All must be ...
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XC4000 Series Field Programmable Gate Arrays Table 18: Pin Descriptions (Continued) I/O I/O During After Pin Name Config. Config. TDO O O I/O TDI, TCK TMS (JTAG) HDC O I/O LDC O I/O INIT I/O I/O PGCK1 ...
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Table 18: Pin Descriptions (Continued) I/O I/O During After Pin Name Config. Config. These four inputs are used in Asynchronous Peripheral mode. The chip is selected when CS0 is Low and CS1 is High. While the chip is selected, a ...
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XC4000 Series Field Programmable Gate Arrays Boundary Scan The ‘bed of nails’ has been the traditional method of testing electronic assemblies. This approach has become less appropriate, due to closer pin spacing and more sophisti- cated assembly methods like surface-mount ...
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TS/OE 3-State TS Boundary OUTPUT INVERT OUTPUT M Ouput Data O Ouput Clock OK M Clock Enable capture Boundary Scan I - update DELAY M Input Clock IK INPUT GLOBAL S/R Figure 42: Block Diagram of XC4000E ...
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XC4000 Series Field Programmable Gate Arrays IOB IOB IOB IOB IOB IOB IOB IOB IOB IOB IOB BYPASS REGISTER INSTRUCTION REGISTER TDI M U INSTRUCTION REGISTER TDO X BYPASS REGISTER IOB IOB IOB IOB IOB IOB IOB IOB IOB IOB ...
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Bit Sequence The bit sequence within each IOB is: In, Out, 3-State. The input-only M0 and M2 mode pins contribute only the In bit to the boundary scan I/O data register, while the output- only M1 pin contributes all three ...
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XC4000 Series Field Programmable Gate Arrays Configuration Configuration is the process of loading design-specific pro- gramming data into one or more FPGAs to define the func- tional operation of the internal interconnections. This is somewhat like loading the com- mand ...
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CCLK serializes the data. Slave Serial Mode In Slave Serial mode, the FPGA receives serial configura- tion data on the rising edge of CCLK and, after loading its configuration, passes additional data ...
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XC4000 Series Field Programmable Gate Arrays mode runs at eight times the data rate of the other six modes. A length count is not used in Express mode. Express mode must be specifi option to the Make- Bits ...
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Table 22: XC4000E Program Data Device XC4003E XC4005E/L XC4006E Max Logic Gates 3,000 5,000 CLBs 100 (Row x Col.) (10 x 10) (14 x 14) IOBs 80 Flip-Flops 360 Horizontal 20 Longlines TBUFs per 12 Longline Bits per Frame 126 ...
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XC4000 Series Field Programmable Gate Arrays Table 23: XC4000EX Program Data Device Max Logic Gates CLBs (Row x Col.) IOBs Flip-Flops Horizontal Longlines TBUFs per Longline Bits per Frame Frames Program Data PROM Size (bits) Notes: 1. Bits per Frame ...
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Configuration Sequence There are four major steps in the XC4000-Series power-up configuration sequence. • Configuration Memory Clear • Initialization • Configuration • Start-Up The full process is illustrated in Figure Configuration Memory Clear When power is first applied or is ...
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XC4000 Series Field Programmable Gate Arrays Configuration The 0010 preamble code, included for all modes except Express mode, indicates that the following 24 bits repre- sent the length count. The length count is the total number of configuration clocks needed ...
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Length Count Match CCLK DONE I/O XC2000 Global Reset DONE XC3000 I/O Global Reset DONE I/O XC4000E/EX CCLK_NOSYNC GSR Active DONE I/O XC4000E/EX CCLK_SYNC GSR Active DONE I/O XC4000E/EX UCLK_NOSYNC GSR Active DONE I/O XC4000E/EX UCLK_SYNC GSR Active Synchronization Uncertainty ...
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XC4000 Series Field Programmable Gate Arrays The XC4000 Series offers another start-up clocking option, UCLK_NOSYNC. The three events described above need not be triggered by CCLK. They can configuration option, be triggered by a user clock. This means ...
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Q3 Q1/Q4 STARTUP DONE FULL S Q LENGTH COUNT K CLEAR MEMORY CCLK 0 STARTUP.CLK 1 USER NET CONFIGURATION BIT OPTIONS SELECTED BY USER IN ...
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XC4000 Series Field Programmable Gate Arrays Configuration Through the Boundary Scan Pins XC4000-Series devices can be configured through the boundary scan pins. The basic procedure is as follows: • Power up the FPGA with INIT held Low (or drive the ...
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Readback Options Readback options are: Read Capture, Read Abort, and Clock Select. They are set with MakeBits, the bitstream generation software. Read Capture When the Read Capture option is selected, the readback data stream includes sampled values of CLB and ...
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XC4000 Series Field Programmable Gate Arrays Configuration Timing The seven configuration modes are discussed in detail in this section. Timing specifications are included. Master Serial Mode In Master Serial mode, the CCLK output of the lead FPGA drives a Xilinx ...
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CCLK (Output DSCK Serial Data In n Serial DOUT n – 3 (Output) Description DIN setup CCLK DIN hold Notes power-up, Vcc must rise from 2 Vcc min in less than 25 ms, otherwise ...
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XC4000 Series Field Programmable Gate Arrays Slave Serial Mode In Slave Serial mode, an external signal drives the CCLK input of the FPGA. The serial configuration bitstream must be available at the DIN input of the lead FPGA a short ...
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DIN Bit DCC CCLK DOUT (Output) Description DIN setup DIN hold DIN to DOUT CCLK High time Low time Frequency Note: Configuration must be delayed until the INIT pins of all daisy-chained FPGAs are High. Figure 56: ...
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XC4000 Series Field Programmable Gate Arrays Master Parallel Modes In the two Master Parallel modes, the lead FPGA directly addresses an industry-standard byte-wide EPROM, and accepts eight data bits just before incrementing or decre- menting the address outputs. The eight ...
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A0-A17 (output) D0-D7 RCLK (output) CCLK (output) DOUT (output) Description Delay to Address valid RCLK Data setup time Data hold time Notes power-up, Vcc must rise from 2 Vcc min in less than 25 ms, otherwise ...
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XC4000 Series Field Programmable Gate Arrays Synchronous Peripheral Mode Synchronous Peripheral mode can also be considered Slave Parallel mode. An external signal drives the CCLK input(s) of the FPGA(s). The first byte of parallel configura- tion data must be available ...
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CCLK INIT BYTE 0 DOUT RDY/BUSY Description INIT (High) setup time setup time hold time CCLK CCLK High time CCLK Low time CCLK Frequency Notes: 1. Peripheral Synchronous mode can be considered Slave Parallel ...
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XC4000 Series Field Programmable Gate Arrays Asynchronous Peripheral Mode Write to FPGA Asynchronous Peripheral mode uses the trailing edge of the logic AND condition of WS and CS0 being Low and RS and CS1 being High to accept byte-wide data ...
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Write to LCA WS/CS0 RS, CS1 D0-D7 CCLK 4 T WTRB RDY/BUSY DOUT Description Effective Write time (CS0, WS=Low; RS, CS1=High) Write DIN setup time DIN hold time RDY/BUSY delay after end of Write ...
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XC4000 Series Field Programmable Gate Arrays Express Mode (XC4000EX only) Express mode is similar to Slave Serial mode, except that data is processed one byte per CCLK cycle instead of one bit per CCLK cycle. An external source is used ...
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Description INIT (High) setup time setup time hold time CCLK CCLK High time CCLK Low time CCLK Frequency CCLK INIT D0-D7 DOUT RDY/BUSY CS1 Note: If not driven by the preceding ...
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XC4000 Series Field Programmable Gate Arrays Table 24: Pin Functions During Configuration CONFIGURATION MODE <M2:M1:M0> SYNCH. SLAVE MASTER PERIPH- SERIAL SERIAL <1:1:1> <0:0:0> <0:1:1> M2(HIGH) (I) M2(LOW) (I) M2(LOW) (I) M1(HIGH) (I) M1(LOW) (I) M1(HIGH) (I) M0(HIGH) (I) M0(LOW) (I) ...
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Configuration Switching Characteristics T Vcc POR PROGRAM INIT CCLK OUTPUT or INPUT X1532 Master Modes Description Power-On Reset Program Latency CCLK (output) Delay CCLK (output) Period, slow CCLK (output) Period, fast Slave and Peripheral Modes Description Power-On Reset Program Latency ...
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XC4000 Series Field Programmable Gate Arrays XC4000E Switching Characteristics Definition of Terms In the following tables, some specifications may be designated as Advance or Preliminary. These terms are defined as follows: Advance: Initial estimates based on simulation and/or extrapolation from ...
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XC4000E Absolute Maximum Ratings Symbol V Supply voltage relative to GND CC V Input voltage relative to GND (Note Voltage applied to 3-state output (Note Storage temperature (ambient) STG T Maximum soldering temperature (10 ...
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XC4000 Series Field Programmable Gate Arrays XC4000E Global Buffer Switching Characteristic Guidelines Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are not measured directly. They are ...
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XC4000E Wide Decoder Switching Characteristic Guidelines Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are not measured directly. They are derived from benchmark timing patterns that ...
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XC4000 Series Field Programmable Gate Arrays XC4000E Horizontal Longline Switching Characteristic Guidelines Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are not measured directly. They are ...
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XC4000E CLB Switching Characteristic Guidelines Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are not measured directly. They are derived from benchmark timing patterns that are ...
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XC4000 Series Field Programmable Gate Arrays XC4000E CLB Switching Characteristic Guidelines (continued) Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are not measured directly. They are ...
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XC4000E CLB Edge-Triggered (Synchronous) RAM Switching Characteristic Guidelines Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are not measured directly. They are derived from benchmark timing ...
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XC4000 Series Field Programmable Gate Arrays XC4000E CLB Edge-Triggered (Synchronous) Dual-Port RAM Switching Characteristic Guidelines Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are not measured ...
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XC4000E CLB Level-Sensitive RAM Switching Characteristic Guidelines Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are not measured directly. They are derived from benchmark timing patterns ...
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XC4000 Series Field Programmable Gate Arrays XC4000E CLB Level-Sensitive RAM Timing Characteristics ADDRESS WRITE WRITE ENABLE DATA IN READ WITHOUT WRITE X,Y OUTPUTS VALID READ, CLOCKING DATA INTO FLIP-FLOP CLOCK XQ, YQ OUTPUTS READ DURING WRITE WRITE ENABLE DATA IN ...
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XC4000E Guaranteed Input and Output Parameters (Pin-to-Pin, TTL I/O) All values listed below are tested directly, and guaranteed over the operating conditions. The same parameters can also be derived indirectly from the IOB and Global Buffer specifications. The XACT delay ...
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XC4000 Series Field Programmable Gate Arrays XC4000E IOB Input Switching Characteristic Guidelines Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are not measured directly. They are ...
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XC4000E IOB Input Switching Characteristic Guidelines (continued) Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are not measured directly. They are derived from benchmark timing patterns ...
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XC4000 Series Field Programmable Gate Arrays XC4000E IOB Output Switching Characteristic Guidelines Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are not measured directly. They are ...
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XC4000E IOB Output Switching Characteristic Guidelines (continued) Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are not measured directly. They are derived from benchmark timing patterns ...
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XC4000 Series Field Programmable Gate Arrays XC4000E Boundary Scan (JTAG) Switching Characteristic Guidelines Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are not measured directly. They ...
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Device-Specific Pinout Tables Pin Locations for XC4003E Devices The following table may contain pinout information for unsupported device/package combinations. Please see the availability charts elsewhere in the XC4000 Series data sheet for availability information. XC4003E Pad Name ...
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XC4000 Series Field Programmable Gate Arrays Pin Locations for XC4005E/L Devices The following table may contain pinout information for unsupported device/package combinations. Please see the availability charts elsewhere in the XC4000 Series data sheet for availability information. XC4005 PC PQ ...
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XC4005 E/L 84 100 144 156 Pad Name I/O, P51 P51 P70 R16 P78 P100 SGCK3 GND P52 P52 P71 P14 DONE P53 P53 P72 R15 P80 P103 VCC P54 P54 P73 P13 PRO- P55 P55 ...
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XC4000 Series Field Programmable Gate Arrays Pin Locations for XC4006E Devices The following table may contain pinout information for unsupported device/package combinations. Please see the availability charts elsewhere in the XC4000 Series data sheet for availability information. XC4006E PC TQ ...
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XC4006E Pad Name 84 144 156 160 GND P52 P71 P14 P79 DONE P53 P72 R15 P80 VCC P54 P73 P13 P81 PROGRAM P55 P74 R14 P82 I/O (D7) P56 P75 T16 P83 I/O, PGCK3 P57 P76 ...
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XC4000 Series Field Programmable Gate Arrays Pin Locations for XC4008E Devices The following table may contain pinout information for unsupported device/package combinations. Please see the availability charts elsewhere in the XC4000 Series data sheet for availability information XC4008E ...
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PC PQ XC4008E Pad Name 84 160 GND - P70 I/O - P71 I/O - P72 I/O P48 P73 I/O P49 P74 I/O - P75 I/O - P76 I/O P50 P77 I/O, SGCK3 P51 P78 GND P52 P79 DONE P53 ...
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XC4000 Series Field Programmable Gate Arrays Pin Locations for XC4010E/L Devices The following table may contain pinout information for unsupported device/package combinations. Please see the availability charts elsewhere in the XC4000 Series data sheet for availability information. XC4010E ...
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XC4010E Pad Name 84 160 176 191 I/O - P53 P57 F18 P69 I/O P38 P54 P58 G17 P70 I/O P39 P55 P59 G18 P71 I P60 H16 P72 I P61 H17 ...
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XC4000 Series Field Programmable Gate Arrays XC4010E Pad Name 84 160 176 191 I/O - P126 P138 R2 P164 C12 I/O P79 P127 P139 T2 P165 A13 (CS1, A2) I/O (A3) P80 P128 P140 N3 P166 ...
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Pin Locations for XC4013E/L Devices The following table may contain pinout information for unsupported device/package combinations. Please see the availability charts elsewhere in the XC4000 Series data sheet for availability information. PQ/ XC4013E Pad Name 160 223 ...
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XC4000 Series Field Programmable Gate Arrays PQ/ XC4013E Pad Name 160 223 208 I E15 I F15 GND P51 P67 G16 I/O P52 P68 E18 I/O P53 P69 F18 I/O P54 P70 G17 ...
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PQ/ XC4013E Pad Name 160 223 208 O, TDO P121 P159 U2 GND P122 P160 R3 I/O P123 P161 T3 (A0, WS) I/O, PGCK4 P124 P162 U1 (A1) I/O P125 P163 P3 I/O P126 P164 R2 I/O ...
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XC4000 Series Field Programmable Gate Arrays Pin Locations for XC4020E Devices The following table may contain pinout information for unsupported device/package combinations. Please see the availability charts elsewhere in the XC4000 Series data sheet for availability information. HQ XC4020E Pad ...
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HQ PG XC4020E Pad Name 208 223 VCC P55 D16 I (M2) P56 C16 I/O, PGCK2 P57 B17 I/O (HDC) P58 E16 I/O P59 C17 I/O P60 D17 I/O P61 B18 I/O (LDC) P62 E17 I I/O - ...
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XC4000 Series Field Programmable Gate Arrays HQ XC4020E Pad Name 208 I/O P136 I/O P137 I/O - I/O - I/O (D2) P138 I/O P139 VCC - I/O P140 I/O P141 I/O - I/O - GND P142 I/O - I/O - ...
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Pin Locations for XC4025E, XC4028EX, & XC4028XL Devices The following table may contain pinout information for unsupported device/package combinations. Please see the availability charts elsewhere in the XC4000 Series data sheet for availability information. XC4025E /28EX/XL ...
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XC4000 Series Field Programmable Gate Arrays XC4025E /28EX/XL 208 223 240 299 Pad Name I/O P33 B11 P41 A14 I/O P34 A12 P42 C13 I/O P35 B12 P43 B14 I/O, FCLK2 P36 A13 P44 D13 GND ...
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XC4025E /28EX/XL 208 223 240 299 Pad Name I/O P97 R17 P115 R16 I/O P98 P16 P116 T17 I/O P99 U18 P117 U18 I/O, SGCK3, P100 T16 P118 X20 GCK4 GND P101 R16 P119 W20 P154 ...
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XC4000 Series Field Programmable Gate Arrays XC4025E /28EX/XL 208 223 240 299 Pad Name I I VCC - - - GND - - - I P189 ...
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Additional No Connect, Vcc & Ground Connections on BG352 Package N.C. VCC A18 A10 A24 A17 B4 B2 B10 B25 B23 D7 C1 D13 C5 D19 C8 G23 C11 D16 K26 D25 N23 F23 P4 J26 U1 ...
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XC4000 Series Field Programmable Gate Arrays Pin Locations for XC4036EX/XL Devices The following table may contain pinout information for unsupported device/package combinations. Please see the availability charts elsewhere in the XC4000 Series data sheet for availability information. XC4036EX/XL HQ304 PG411 ...
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XC4036EX/XL HQ304 PG411 BG432 Pad Name I (M0) P229 E35 VCC P228 VCC* I (M2) P227 G33 I/O, GCK3 P226 D36 I/O (HDC) P225 C37 I/O P224 F34 I/O P223 J33 I/O P222 D38 I/O (LDC) P221 G35 I/O - ...
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XC4000 Series Field Programmable Gate Arrays XC4036EX/XL HQ304 PG411 BG432 Pad Name I/O, GCK5 P149 AP34 I/O P148 AW39 I/O P147 AN31 I/O - AV36 I/O - AR33 I/O P146 AP32 I/O P145 AU35 I/O P144 AW33 I/O P143 AU33 ...
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XC4036EX/XL HQ304 PG411 BG432 Pad Name I/O - AR3 I/O - AR1 I/O (CS1, A2) P70 AK6 I/O (A3) P69 AN3 I/O P68 AM6 I/O P67 AM2 VCC - VCC* GND - GND* I/O P66 AL3 I/O P65 AH6 I/O ...
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XC4000 Series Field Programmable Gate Arrays Additional No Connect (N.C.) Connections on HQ304 Package N.C. P11 P24 P53 P100 P128 3/22/96 Additional No Connect, Vcc & Ground Connections on PG411 Package N.C. N.C. VCC A13 AA37 B6 AB2 A11 B34 ...
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Pin Locations for XC4044EX/XL Devices The following table may contain pinout information for unsupported device/package combinations. Please see the availability charts elsewhere in the XC4000 Series data sheet for availability information. XC4044EX/XL PG411 BG432 Pad Name GND GND* GND* I/O, ...
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XC4000 Series Field Programmable Gate Arrays XC4044EX/XL PG411 Pad Name VCC VCC* I (M2) G33 I/O, GCK3 D36 I/O (HDC) C37 I/O F34 I/O J33 I/O D38 I/O (LDC) G35 I/O E39 I/O K34 I/O F38 I/O G37 VCC VCC* ...
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XC4044EX/XL PG411 BG432 Pad Name I/O AV36 I/O AR33 I/O AP32 I/O AU35 I/O AW33 I/O AU33 VCC VCC* VCC* GND GND* GND* I/O (D6) AV32 I/O AU31 I/O AR31 I/O AP28 I/O AP30 I/O AT30 I/O AT32 I/O AV30 ...
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XC4000 Series Field Programmable Gate Arrays XC4044EX/XL PG411 Pad Name I/O AM6 I/O AM2 VCC VCC* GND GND* I/O AL3 I/O AH6 I/O AP2 I/O AK4 I/O AN1 I/O AK2 I/O AG5 I/O AF6 I/O AL5 I/O AJ3 GND GND* ...
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Additional No Connect, Vcc & Ground Connections on PG411 Package N.C. VCC A13 A3 B6 A11 B34 A21 C25 A31 C33 C39 D12 D6 E7 F36 E23 J1 E37 L39 AA39 H34 AJ1 L35 AL39 N3 AP4 ...
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XC4000 Series Field Programmable Gate Arrays Pin Locations for XC4052XL Devices The following table may contain pinout information for unsupported device/package combinations. Please see the availability charts elsewhere in the XC4000 Series data sheet for availability information. XC4052XL Pad Name ...
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XC4052XL Pad Name PG411 BG432 Bndry Scan I/O D30 AD31 I/O D32 AD30 I/O F28 AD29 I/O F30 AD28 I/O C31 AE30 I/O E31 AE29 GND GND* GND* VCC VCC* VCC* I/O B32 AF31 I/O A33 AE28 I/O C33 AF30 ...
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XC4000 Series Field Programmable Gate Arrays XC4052XL Pad Name PG411 I/O AE39 I/O AM36 I/O AC35 I/O AL35 I/O AF38 GND GND* I/O AG39 I/O AG37 VCC VCC* I/O AD34 I/O AN39 I/O AE35 I/O AH38 GND GND* I/O AJ37 ...
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XC4052XL Pad Name PG411 BG432 Bndry Scan I/O (D4) AP20 I/O AU21 VCC VCC* VCC* GND GND* GND* I/O (D3) AU19 I/O (RS) AV20 I/O AV18 I/O AR19 GND GND* GND* I/O AT18 I/O AW17 I/O AV16 I/O AP18 I/O ...
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XC4000 Series Field Programmable Gate Arrays XC4052XL Pad Name PG411 I/O AG1 GND GND* I/O AF2 I/O AJ5 I/O AC5 I/O AE1 I/O AH4 I/O AB6 GND GND* VCC VCC* I/O (A4) AD2 I/O (A5) AB4 I/O AE3 I/O AC1 ...
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Additional Vcc & Ground Connections on PG411 Package VCC A3 A11 A21 A31 C39 D6 F36 J1 L39 W1 AA39 AJ1 AL39 AP4 AT34 AU1 AW9 AW19 AW29 AW37 8/23/96 September 18, 1996 (Version 1.04) Additional No Connect, Vcc & ...
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... I/O P82 I/O (A5) I/O I/O P83 I/O (A6) I/O I/O P84 I/O (A7) I/O (INIT) I/O (INIT) VCC VCC 2/28/96 XC4005E XC4006E XC4008E XC4005L GND GND GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O ...
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PQ100 Package Pinouts The following table may contain pinout information for unsupported device/package combinations. Please see the availability charts elsewhere in the XC4000 Series data sheet for availability information. PQ100 Pin XC4003E P1 I/O (A14) P2 I/O, SGCK1 (A15) P3 ...
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XC4000 Series Field Programmable Gate Arrays VQ100 Package Pinouts The following table may contain pinout information for unsupported device/package combinations. Please see the availability charts elsewhere in the XC4000 Series data sheet for availability information. VQ100 Pin P1 P2 I/O, ...
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PG120 Package Pinouts The following table may contain pinout information for unsupported device/package combinations. Please see the availability charts elsewhere in the XC4000 Series data sheet for availability information. PG120 Pin XC4003E N13 I/O, PGCK3 N12 N11 N10 I/O (CS0) ...
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XC4000 Series Field Programmable Gate Arrays PG120 Pin B13 B12 B11 B10 I/O, PGCK1 (A16) B1 A13 4-138 XC4003E PG120 Pin GND VCC I/O (A14) I/O (A12) N.C. ...
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TQ144 Package Pinouts The following table may contain pinout information for unsupported device/package combinations. Please see the availability charts elsewhere in the XC4000 Series data sheet for availability information. TQ144 Pin XC4005E P1 GND P2 I/O, PGCK1 (A16) P3 I/O ...
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XC4000 Series Field Programmable Gate Arrays TQ144 Pin XC4005E P91 GND P92 I/O (D3) P93 I/O (RS) P94 I/O P95 I/O P96 I/O (D2) P97 I/O P98 I/O P99 I/O P100 GND P101 I/O (D1) P102 I/O (RCLK, RDY/BUSY) P103 ...
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PG156 Package Pinouts The following table may contain pinout information for unsupported device/package combinations. Please see the availability charts elsewhere in the XC4000 Series data sheet for availability information. PG156 Pin XC4005E T1 O, TDO T2 I/O, SGCK4 (DOUT) I/O, ...
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XC4000 Series Field Programmable Gate Arrays PG156 Pin XC4005E F1 I/O (A10) F2 I/O (A11) F3 GND F14 GND F15 I/O F16 I/O E1 I/O E2 I/O E3 I/O (A12) E14 I/O E15 N.C. E16 I/O D1 N.C. D2 N.C. ...
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PQ160 Package Pinouts The following table may contain pinout information for unsupported device/package combinations. Please see the availability charts elsewhere in the XC4000 Series data sheet for availability information. PQ 160 XC4005E XC4006E XC4008E XC4010E XC4013E Pin P1 GND GND ...
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XC4000 Series Field Programmable Gate Arrays PQ 160 XC4005E XC4006E XC4008E XC4010E XC4013E Pin P91 GND GND GND P92 I/O I/O I/O P93 I/O I/O I/O P94 I/O (D5) I/O (D5) I/O (D5) P95 I/O (CS0) I/O (CS0) I/O (CS0) ...
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TQ176 Package Pinouts The following table may contain pinout information for unsupported device/package combinations. Please see the availability charts elsewhere in the XC4000 Series data sheet for availability information. TQ176 Pin XC4010L P1 P2 I/O, PGCK1 (A16) P3 I/O (A17) ...
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XC4000 Series Field Programmable Gate Arrays TQ176 Pin P91 P92 P93 P94 P95 P96 P97 P98 P99 P100 P101 P102 P103 P104 P105 P106 P107 P108 P109 P110 P111 P112 P113 P114 P115 P116 P117 P118 P119 P120 P121 P122 ...
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PQ208, HQ208 Package Pinouts The following table may contain pinout information for unsupported device/package combinations. Please see the availability charts elsewhere in the XC4000 Series data sheet for availability information 208 4005 4006 4008 4010 ...
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XC4000 Series Field Programmable Gate Arrays 208 4005 4006 4008 4010 Pin E E/L P88 I/O I/O I/O I/O P89 I/O I/O I/O I/O P90 GND GND GND GND P91 N.C. N.C. N.C. ...
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208 4005 4006 4008 4010 Pin E E/L P174 I/O (A4) I/O (A4) I/O (A4) I/O (A4) I/O (A4) I/O (A4) I/O (A4) P175 I/O (A5) I/O (A5) I/O (A5) I/O (A5) I/O ...
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XC4000 Series Field Programmable Gate Arrays PG223 and PG191 Package Pinouts These two packages have been combined into a single table because of their physical compatibility. The PG191 has the same dimensions as the PG223, but has 32 fewer pins ...
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PG PG XC4008E XC4010E XC4013E 223 191 PG191 PG191 PG223 Pin Pin N3 N3 I/O (A3) I/O (A3) I/O (A3) N4 I/O N15 I/O N16 N16 I/O I/O I/O N17 N17 N.C. I/O I/O N18 N18 I/O I/O I/O M1 ...
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XC4000 Series Field Programmable Gate Arrays PG PG XC4008E XC4010E XC4013E 223 191 PG191 PG191 PG223 Pin Pin C13 C13 I/O I/O I/O C14 C14 I/O I/O I/O C15 C15 O (M1) O (M1) O (M1) C16 C16 I (M2) ...
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BG225 Package Pinouts The following table may contain pinout information for unsupported device/package combinations. Please see the availability charts elsewhere in the XC4000 Series data sheet for availability information. BG225 Pin XC4010E R1 VCC R2 I/O, PGCK2 R3 I/O R4 ...
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XC4000 Series Field Programmable Gate Arrays BG225 Pin XC4010E H11 I/O (RS) H12 I/O (D3) H13 I/O (D4) H14 I/O H15 VCC G1 I/O G2 I/O G3 I/O G4 I/O G5 I/O G6 I/O G7 GND G8 GND G9 GND ...
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PQ240, HQ240 Package Pinouts The following table may contain pinout information for unsupported device/package combinations. Please see the availability charts elsewhere in the XC4000 Series data sheet for availability information. PQ240/ XC4013E XC4020E XC4025E HQ240 Pin XC4013L P1 GND GND ...
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XC4000 Series Field Programmable Gate Arrays PQ240/ XC4013E XC4020E XC4025E HQ240 Pin XC4013L P86 I/O I/O P87 I/O I/O P88 I/O I/O P89 I/O (INIT) I/O (INIT) I/O (INIT) I/O (INIT) P90 VCC VCC P91 GND GND P92 I/O I/O ...
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PQ240/ XC4013E XC4020E XC4025E HQ240 Pin XC4013L P174 I/O I/O (RCLK, (RCLK, (RCLK, RDY/ RDY/ BUSY) BUSY) BUSY) P175 I/O I/O P176 I/O I/O P177 I/O I/O (D0, DIN) (D0, DIN) (D0, DIN) P178 I/O, I/O, SGCK4 SGCK4 SGCK4 (DOUT) ...
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XC4000 Series Field Programmable Gate Arrays PG299 Package Pinouts The following table may contain pinout information for unsupported device/package combinations. Please see the availability charts elsewhere in the XC4000 Series data sheet for availability information. PG299 Pin XC4025E X1 I/O, ...
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PG299 Pin XC4025E R1 VCC R2 I/O R3 I/O R4 I/O R5 I/O R16 I/O R17 I/O R18 I/O R19 I/O R20 GND P1 I/O P2 I/O P3 I/O P4 I/O P5 I/O P16 I/O P17 I/O P18 I/O P19 ...
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XC4000 Series Field Programmable Gate Arrays PG299 Pin XC4025E E7 I/O E8 I/O E9 I/O E10 I/O E11 I/O E12 I/O E13 I/O E14 I/O E15 I/O E16 GND E17 I/O E18 I/O E19 I/O E20 GND D1 I/O D2 ...
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HQ304 Package Pinouts The following table may contain pinout information for unsupported device/package combinations. Please see the availability charts elsewhere in the XC4000 Series data sheet for availability information. HQ304 XC4028EX XC4025E Pin XC4028XL P1 VCC VCC P2 I/O, SGCK1 ...
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XC4000 Series Field Programmable Gate Arrays HQ304 XC4028EX XC4025E Pin XC4028XL P99 I/O I/O P100 N.C. N.C. P101 VCC VCC P102 I/O I/O P103 I/O (D2) I/O (D2) P104 I/O I/O P105 I/O I/O P106 I/O I/O P107 I/O I/O ...
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HQ304 XC4028EX XC4025E Pin XC4028XL P205 N.C. N.C. P206 I/O I/O P207 I/O I/O P208 I/O I/O P209 I/O I/O P210 GND GND P211 I/O I/O P212 I/O I/O P213 I/O I/O P214 I/O I/O P215 I/O I/O P216 I/O ...
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XC4000 Series Field Programmable Gate Arrays BG352 Package Pinouts The following table may contain pinout information for unsupported device/package combinations. Please see the availability charts elsewhere in the XC4000 Series data sheet for availability information. BG352 Pin XC4028EX/XL AF1 AF2 ...
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BG352 Pin XC4028EX/XL AA4 AA23 AA24 AA25 AA26 I/O (D6) Y4 Y23 Y24 Y25 Y26 W23 W24 W25 W26 V1 I/O (CS0) V2 I/O (D5 V23 V24 V25 V26 U1 U2 ...
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XC4000 Series Field Programmable Gate Arrays BG352 Pin XC4028EX/XL F24 F25 F26 I/O, GCK6 (DOUT) E23 E24 E25 E26 D10 D11 D12 D13 D14 D15 D16 D17 ...
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PG411 Package Pinouts The following table may contain pinout information for unsupported device/package combinations. Please see the availability charts elsewhere in the XC4000 Series data sheet for availability information. PG411 Pin XC4036EX/XL XC4044EX/XL AW1 I/O I/O AW3 GND GND AW5 ...
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XC4000 Series Field Programmable Gate Arrays PG411 Pin XC4036EX/XL XC4044EX/XL AP6 I/O (D0, DIN) I/O (D0, DIN) AP8 N.C. N.C. AP10 I/O I/O AP12 I/O I/O AP14 I/O I/O AP16 I/O I/O AP18 I/O I/O AP20 I/O (D4) I/O (D4) ...
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PG411 Pin XC4036EX/XL XC4044EX/XL Y38 N.C. I/O W1 VCC VCC W3 I/O (A8) I/O (A8) W5 N.C. I/O W35 N.C. I/O W37 I/O (INIT) I/O (INIT) W39 GND GND V2 N.C. I/O V4 I/O (A19) I/O (A19) V6 I/O I/O ...
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XC4000 Series Field Programmable Gate Arrays PG411 Pin XC4036EX/XL XC4044EX/XL E5 I/O (A14) I/O (A14) E7 N.C. N.C. E9 I/O I/O E11 I/O, TMS I/O, TMS E13 I/O I/O E15 I/O I/O E17 I/O I/O E19 I/O I/O E21 I/O ...
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BG432 Package Pinouts The following table may contain pinout information for unsupported device/package combinations. Please see the availability charts elsewhere in the XC4000 Series data sheet for availability information. BG432 Pin XC4036EX XC4044EX XC4036XL XC4044XL AL1 VCC VCC AL2 GND ...
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XC4000 Series Field Programmable Gate Arrays BG432 Pin XC4036EX XC4044EX XC4036XL XC4044XL AH16 GND GND AH17 I/O I/O AH18 I/O I/O AH19 N.C. N.C. AH20 I/O I/O AH21 VCC VCC AH22 I/O I/O AH23 N.C. I/O AH24 I/O I/O AH25 ...
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BG432 Pin XC4036EX XC4044EX XC4036XL XC4044XL R3 I/O I/O R4 I/O I/O R28 I/O I/O R29 I/O I/O R30 I/O I/O R31 I/O I/O P1 GND GND P2 I/O I/O P3 I/O I/O P4 I/O I/O P28 I/O I/O P29 ...
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XC4000 Series Field Programmable Gate Arrays BG432 Pin XC4036EX XC4044EX XC4036XL XC4044XL D27 I/O I/O D28 I/O, GCK8 (A15) I/O, GCK8 (A15) I/O, GCK8 (A15) D29 I/O, GCK1 (A16) I/O, GCK1 (A16) I/O, GCK1 (A16) D30 I/O, TDI I/O, TDI ...
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Product Availability Table 25 - Table 27 show the planned packages and speed grades for XC4000-Series devices. Call your local sales office for the latest availability information, or see the Xilinx W specifications. Table 25: Component Availability Chart for XC4000E ...
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... Industrial -40 to +100 Mil Temp -55 to +125 MIL-STD-883C Class -55 to +125 C C Shaded device/package combinations are not supported. Table 27: Component Availability Chart for XC4000L and XC4000XL FPGAs Speed PC TQ Grade 84 176 -6 C XC4005L - XC4010L - XC4013L -5 -4 XC4028XL XC4036XL XC4044XL XC4052XL XC4062XL ...
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User I/O Per Package Maximum available user I/O for each device/package combination is shown in Pinout tables for XC4000-Series devices follow. Pinout data is offered in two forms, as device-specific and package-specific tables. Device-specific tables include all packages for each ...
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... M1 and TDO pins can be used as outputs only. All of these pins must be called out using special library symbols. The XACT software does not use them by default. (See Table 30: Maximum User I/O for XC4000L and XC4000XL Device/Package Combinations No. of Package XC4005L XC4010L XC4013L XC4028XL XC4036XL XC4044XL XC4052XL XC4062XL Pins (Code) Maximum User I/O 112 ...
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Ordering Information Example: XC4013E-3HQ240C Device Type Speed Grade - Plastic Lead Chip Carrier PQ = Plastic Quad Flat Pack VQ = Very Thin Quad Flat Pack TQ = Thin Quad Flat Pack September 18, ...