XC5VLX110-1FFG676C Xilinx Inc, XC5VLX110-1FFG676C Datasheet - Page 306
XC5VLX110-1FFG676C
Manufacturer Part Number
XC5VLX110-1FFG676C
Description
IC FPGA VIRTEX-5 110K 676FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 LXr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VLX110-1FFG676C
Total Ram Bits
4718592
Number Of Logic Elements/cells
110592
Number Of Labs/clbs
8640
Number Of I /o
440
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
676-BBGA, FCBGA
No. Of Logic Blocks
17280
No. Of Gates
110000
Family Type
Virtex-5 LX
No. Of Speed Grades
1
No. Of I/o's
440
Clock Management
PLL
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
HW-V5-ML523-UNI-G - EVALUATION PLATFORM VIRTEX-5
Number Of Gates
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
122-1557
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Chapter 6: SelectIO Resources
306
Nominal PCB Specifications
PCB Construction
Signal Return Current Management
Load Traces
Power Distribution System Design
The nominal SSO table
parameters meet the following requirements.
Note:
SSO Calculator must be used to determine the SSO limit, according to the physical factors of the
unique PCB.
•
•
•
•
•
•
•
•
•
V
Total board thickness must be no greater than 62 mils (1575 µ).
Traces must be referenced to a plane on an adjacent PCB layer.
The reference plane must be either GND or the V
driver.
The reference layer must remain uninterrupted for its full length from device to
device.
All IOB output buffers must drive controlled impedance traces with characteristic
impedance of 50Ω ± 10%.
Total capacitive loading at the far end of the trace (input capacitance of receiving
device) must be no more than 10 pF.
Designed according to the Virtex-5 FPGA PCB Designer’s Guide.
•
•
V
CCO
CCO
In cases where PCB parameters do not meet all requirements listed below, the Virtex-5 FPGA
Decoupling capacitors per the device guideline
Approved solder land patterns
and GND vias should have a drill diameter no less than 11 mils (279 µ).
and GND planes cannot be separated by more than 5.0 mils (152 µ)
(Table
www.xilinx.com
6-40) contains SSO limits for cases where the PCB
CCO
associated with the output
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
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