XC5VLX110-1FFG676C Xilinx Inc, XC5VLX110-1FFG676C Datasheet - Page 74

• Manufacturer Part Number: XC5VLX110-1FFG676C
• Description: IC FPGA VIRTEX-5 110K 676FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXr

Specifications of XC5VLX110-1FFG676C

• Total Ram Bits: 4718592
• Number Of Logic Elements/cells: 110592
• Number Of Labs/clbs: 8640
• Number Of I /o: 440
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 676-BBGA, FCBGA
• No. Of Logic Blocks: 17280
• No. Of Gates: 110000
• Family Type: Virtex-5 LX
• No. Of Speed Grades: 1
• No. Of I/o's: 440
• Clock Management: PLL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: HW-V5-ML523-UNI-G - EVALUATION PLATFORM VIRTEX-5
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 122-1557

Chapter 2: Clock Management Technology
74
PLL To and From DCM
DCM To and From PMCD
Figure 2-7
same CMT block. The PLL can drive either DCM in the same CMT block using a dedicated
connection. Similarly, the DCM can drive the PLL within the same CMT block with a
dedicated connection. There is no BUFGCTRL required between the PLL and the DCM.
X-Ref Target - Figure 2-7
The PMCD block is not available in the Virtex-5 devices. However, a limited retargeting
using the PLL is possible. Refer to
for more information.
From any IBUFG implementation
From any BUFG implementation
summarizes the dedicated connection between the DCM and the PLL in the
Figure 2-7: DCM and PLL Connection in Same CMT Block
www.xilinx.com
PLL in Virtex-4 FPGA PMCD Legacy Mode in Chapter 3
PLL to DCM Input
CLKFBIN
PLL to DCM Input
CLKFB
DCM to PLL Input
CLKIN
DCM to PLL Input
CLKFB
CLKIN
CLKIN
DCM2
DCM1
PLL
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
Routing (BUFG)
Routing (BUFG)
Routing (BUFG)
To Global
ug190_2_07_072307
To Global
To Global