EP3C5E144I7N Altera, EP3C5E144I7N Datasheet - Page 19
EP3C5E144I7N
Manufacturer Part Number
EP3C5E144I7N
Description
IC CYCLONE III FPGA 5K 144 EQFP
Manufacturer
Altera
Series
Cyclone® IIIr
Datasheets
1.EP3C5F256C8N.pdf
(5 pages)
2.EP3C5F256C8N.pdf
(34 pages)
3.EP3C5F256C8N.pdf
(66 pages)
4.EP3C5F256C8N.pdf
(14 pages)
5.EP3C5F256C8N.pdf
(76 pages)
6.EP3C5E144I7N.pdf
(274 pages)
Specifications of EP3C5E144I7N
Number Of Logic Elements/cells
5136
Number Of Labs/clbs
321
Total Ram Bits
423936
Number Of I /o
94
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
144-EQFP
Family Name
Cyclone III
Number Of Logic Blocks/elements
5136
# I/os (max)
94
Frequency (max)
437.5MHz
Process Technology
65nm
Operating Supply Voltage (typ)
1.2V
Logic Cells
5136
Ram Bits
423936
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
144
Package Type
EQFP
For Use With
544-2601 - KIT DEV CYCLONE III LS EP3CLS200544-2411 - KIT DEV NIOS II CYCLONE III ED.
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-2557
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP3C5E144I7N
Manufacturer:
Altera
Quantity:
135
Company:
Part Number:
EP3C5E144I7N
Manufacturer:
ALTERA32
Quantity:
345
Part Number:
EP3C5E144I7N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Chapter 1: Cyclone III Device Data Sheet
Switching Characteristics
Table 1–26. Cyclone III Devices RSDS Transmitter Timing Specifications
Table 1–27. Cyclone III Devices Emulated RSDS_E_1R Transmitter Timing Specifications
© January 2010 Altera Corporation
Device operation in
Mbps
t
TCCS
Output jitter
(peak to peak)
t
t
t
Notes to
(1) Applicable for true RSDS and emulated RSDS_E_3R transmitter.
(2) True RSDS transmitter is only supported at output pin of Row I/O (Banks 1, 2, 5, and 6). Emulated RSDS transmitter is supported at the output
(3) t
f
clock
frequency)
Device
operation in
Mbps
t
TCCS
Output jitter
(peak to
peak)
DUTY
RISE
FALL
LOCK
HSC LK
DUTY
Symbol
(3)
pin of all I/O banks.
LOC K
(input
Symbol
Table
is the time required for the PLL to lock from the end of device configuration.
1–26:
Modes
×10
×10
×8
×7
×4
×2
×1
×8
×7
×4
×2
×1
—
—
—
20 – 80%, C
20 – 80%, C
Modes
×10
×8
×7
×4
×2
×1
—
—
—
—
Min
100
10
10
10
10
10
10
80
70
40
20
10
45
—
—
LOA D
LOA D
= 5 pF
= 5 pF
Typ
C6
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Min
100
80
70
40
20
10
45
—
—
—
—
—
Max
170
170
170
170
170
170
170
200
500
85
85
85
85
85
55
500
500
Typ
C6
—
—
—
—
—
—
—
—
—
—
Min
100
Max
360
360
360
360
360
360
200
500
10
10
10
10
10
10
80
70
40
20
10
45
—
—
55
—
—
1
C7, I7
Min
100
80
70
40
20
10
45
—
—
—
—
—
Typ
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
(Note
C7, I7
500
500
Typ
—
—
—
—
—
—
—
—
—
—
Max
170
170
170
170
170
170
170
200
500
85
85
85
85
85
55
1),
Max
(2)
311
311
311
311
311
311
200
500
55
—
—
1
(Note 1)
Min
100
10
10
10
10
10
10
80
70
40
20
10
45
—
—
Cyclone III Device Handbook, Volume 2
(Part 2 of 2)
Min
100
80
70
40
20
10
45
—
—
—
—
—
C8, A7
Typ
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
(Part 1 of 2)
C8, A7
500
500
Typ
—
—
—
—
—
—
—
—
—
—
Max
170
170
170
170
170
170
170
200
550
85
85
85
85
85
55
Max
311
311
311
311
311
311
200
550
55
—
—
1
Mbps
Mbps
Mbps
Mbps
Mbps
Mbps
MHz
MHz
MHz
MHz
MHz
MHz
Unit
Mbps
Mbps
Mbps
Mbps
Mbps
Mbps
%
ps
ps
Unit
ms
%
ps
ps
ps
ps
1–19