EPF6024ATC144-3N Altera, EPF6024ATC144-3N Datasheet - Page 13

• Manufacturer Part Number: EPF6024ATC144-3N
• Description: IC FLEX 6000 FPGA 24K 144-TQFP
• Manufacturer: Altera
• Series: FLEX 6000r

Specifications of EPF6024ATC144-3N

• Number Of Logic Elements/cells: 1960
• Number Of Labs/clbs: 196
• Number Of I /o: 117
• Number Of Gates: 24000
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 144-TQFP, 144-VQFP
• Family Name: FLEX 6000
• Number Of Usable Gates: 24000
• Number Of Logic Blocks/elements: 1960
• # I/os (max): 117
• Frequency (max): 142.86MHz
• Process Technology: SRAM
• Operating Supply Voltage (typ): 3.3V
• Logic Cells: 1960
• Device System Gates: 24000
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Total Ram Bits: -
• Lead Free Status / Rohs Status: Compliant

Figure 6. Cascade Chain Operation
Altera Corporation
d[(4 n -1)..4( n -1)]
AND Cascade Chain
d[3..0]
d[7..4]
LUT
LUT
LUT
LE Operating Modes
The FLEX 6000 LE can operate in one of the following three modes:
■
■
■
Each of these modes uses LE resources differently. In each mode, seven
available inputs to the LE—the four data inputs from the LAB local
interconnect, the feedback from the programmable register, and the
carry-in and cascade-in from the previous LE—are directed to different
destinations to implement the desired logic function. LAB-wide signals
provide clock, asynchronous clear, synchronous clear, and synchronous
load control for the register. The Altera software, in conjunction with
parameterized functions such as LPM and DesignWare functions,
automatically chooses the appropriate mode for common functions such
as counters, adders, and multipliers. If required, the designer can also
create special-purpose functions to use an LE operating mode for optimal
performance.
Figure 7
Normal mode
Arithmetic mode
Counter mode
shows the LE operating modes.
LE n + 1
LE 2
LE 3
FLEX 6000 Programmable Logic Device Family Data Sheet
d[(4 n -1)..4( n -1)]
OR Cascade Chain
d[3..0]
d[7..4]
LUT
LUT
LUT
LE n + 1
LE 2
LE 3
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