EPF6024ATC144-3N Altera, EPF6024ATC144-3N Datasheet - Page 39

• Manufacturer Part Number: EPF6024ATC144-3N
• Description: IC FLEX 6000 FPGA 24K 144-TQFP
• Manufacturer: Altera
• Series: FLEX 6000r

Specifications of EPF6024ATC144-3N

• Number Of Logic Elements/cells: 1960
• Number Of Labs/clbs: 196
• Number Of I /o: 117
• Number Of Gates: 24000
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 144-TQFP, 144-VQFP
• Family Name: FLEX 6000
• Number Of Usable Gates: 24000
• Number Of Logic Blocks/elements: 1960
• # I/os (max): 117
• Frequency (max): 142.86MHz
• Process Technology: SRAM
• Operating Supply Voltage (typ): 3.3V
• Logic Cells: 1960
• Device System Gates: 24000
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Total Ram Bits: -
• Lead Free Status / Rohs Status: Compliant

Altera Corporation
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OD1
OD2
OD3
XZ
ZX1
ZX2
ZX3
IOE
IN
IN_DELAY
LOCAL
ROW
COL
DIN_D
DIN_C
LEGLOBAL
LABCARRY
LABCASC
Table 20. IOE Timing Microparameters
Table 21. Interconnect Timing Microparameters
Table 22. External Reference Timing Parameters
1
DRR
Symbol
Symbol
Symbol
Output buffer and pad delay, slow slew rate = off, V
Output buffer and pad delay, slow slew rate = off, V
Output buffer and pad delay, slow slew rate = on
Output buffer disable delay
Output buffer enable delay, slow slew rate = off, V
Output buffer enable delay, slow slew rate = off, V
IOE output buffer enable delay, slow slew rate = on
Output enable control delay
Input pad and buffer to FastTrack Interconnect delay
Input pad and buffer to FastTrack Interconnect delay with additional delay
turned on
LAB local interconnect delay
Row interconnect routing delay
Column interconnect routing delay
Dedicated input to LE data delay
Dedicated input to LE control delay
LE output to LE control via internally-generated global signal delay
Routing delay for the carry-out of an LE driving the carry-in signal of a
different LE in a different LAB
Routing delay for the cascade-out signal of an LE driving the cascade-in
signal of a different LE in a different LAB
Register-to-register test pattern
Register-to-register delay via 4 LEs, 3 row interconnects, and 4 local
interconnects
Note (1)
FLEX 6000 Programmable Logic Device Family Data Sheet
Parameter
Parameter
Parameter
Note (1)
CCIO
CCIO
CCIO
CCIO
= V
= low voltage
= V
= low voltage
CCINT
CCINT
C1 = 35 pF
C1 = 35 pF
C1 = 35 pF
C1 = 5 pF
C1 = 35 pF
C1 = 35 pF
C1 = 35 pF
(5)
(5)
(5)
(5)
(6)
(7)
Conditions
Conditions
Conditions
(2)
(3)
(4)
(2)
(3)
(4)
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