EP3C25F256C8N Altera, EP3C25F256C8N Datasheet - Page 70
![IC CYCLONE III FPGA 25K 256-FBGA](/photos/6/70/67063/544-256-fbga_sml.jpg)
EP3C25F256C8N
Manufacturer Part Number
EP3C25F256C8N
Description
IC CYCLONE III FPGA 25K 256-FBGA
Manufacturer
Altera
Series
Cyclone® IIIr
Datasheets
1.EP3C5F256C8N.pdf
(5 pages)
2.EP3C5F256C8N.pdf
(34 pages)
3.EP3C5F256C8N.pdf
(66 pages)
4.EP3C5F256C8N.pdf
(14 pages)
5.EP3C5F256C8N.pdf
(76 pages)
Specifications of EP3C25F256C8N
Number Of Logic Elements/cells
24624
Number Of Labs/clbs
1539
Total Ram Bits
608256
Number Of I /o
156
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
256-FBGA
For Use With
544-2601 - KIT DEV CYCLONE III LS EP3CLS200544-2411 - KIT DEV NIOS II CYCLONE III ED.544-2370 - KIT STARTER CYCLONE III EP3C25
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Other names
544-2077
EP3C25F256C8NES
EP3C25F256C8NES
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP3C25F256C8N
Manufacturer:
ALTERA
Quantity:
1
Part Number:
EP3C25F256C8N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
2–26
Glossary
Table 2–39. Glossary (Part 1 of 5)
Cyclone III Device Handbook, Volume 2
Letter
M
D
G
H
N
O
A
B
C
E
F
K
L
I
J
f
GCLK
GCLK PLL
HSIODR
Input Waveforms
for the SSTL
Differential I/O
Standard
JTAG Waveform
HS CLK
Term
—
—
—
—
—
—
—
—
—
—
Table 2–39
V
Captured
High-speed I/O Block: High-speed receiver and transmitter input and output clock frequency.
Input pin directly to the global clock network.
High-speed I/O Block: Maximum and minimum LVDS data transfer rate (HSIODR = 1/TUI).
Input pin to the global clock network through the PLL.
SWING
Driven
Signal
Signal
to be
to be
TMS
TDO
TCK
TDI
lists the glossary for this chapter.
t
JCH
t
t
JSZX
JPZX
t
JCP
t
JSSU
t
JCL
t
JSH
t
t
JPCO
JSCO
t
t
JPSU_TDI
JPSU_TMS
Definitions
—
—
—
—
—
—
—
—
—
—
t
Chapter 2: Cyclone III LS Device Data Sheet
t
JSXZ
JPH
© December 2009 Altera Corporation
t
JPXZ
V
V
V
REF
IH
IL
Glossary