EP3C25F324C8N Altera, EP3C25F324C8N Datasheet - Page 44
![IC CYCLONE III FPGA 25K 324-FBGA](/photos/6/70/67067/544-324-fbga_sml.jpg)
EP3C25F324C8N
Manufacturer Part Number
EP3C25F324C8N
Description
IC CYCLONE III FPGA 25K 324-FBGA
Manufacturer
Altera
Series
Cyclone® IIIr
Datasheets
1.EP3C5F256C8N.pdf
(5 pages)
2.EP3C5F256C8N.pdf
(34 pages)
3.EP3C5F256C8N.pdf
(66 pages)
4.EP3C5F256C8N.pdf
(14 pages)
5.EP3C5F256C8N.pdf
(76 pages)
6.EP3C25F324C8N.pdf
(274 pages)
Specifications of EP3C25F324C8N
Number Of Logic Elements/cells
24624
Number Of Labs/clbs
1539
Total Ram Bits
608256
Number Of I /o
215
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
324-FBGA
Family Name
Cyclone III
Number Of Logic Blocks/elements
24624
# I/os (max)
215
Frequency (max)
402MHz
Process Technology
65nm
Operating Supply Voltage (typ)
1.2V
Logic Cells
24624
Ram Bits
608256
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
324
Package Type
FBGA
For Use With
544-2601 - KIT DEV CYCLONE III LS EP3CLS200544-2411 - KIT DEV NIOS II CYCLONE III ED.544-2370 - KIT STARTER CYCLONE III EP3C25
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-2078
EP3C25F324C8NES
EP3C25F324C8NES
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP3C25F324C8N
Manufacturer:
ALTERA
Quantity:
2 350
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Part Number:
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Manufacturer:
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Quantity:
20 000
Page 44
Validating Pin Placement
f
f
f
■
■
■
The .pof and .jic files are used with the Quartus II Programmer to program the
configuration devices while the .hexout, .rbf, .ttf, and .rpd files are used with other
programmers.
When working with multi-device configuration chains, you should combine each
device’s .sof file into one configuration file in the Convert Programming Files dialog
box. When generating the configuration file, ensure that the configuration files are in
the same order as the devices on the board.
For more information about setting device configuration options or creating
configuration files, refer to the
Configuration Handbook.
For more information about programming file formats and using the programmer,
refer to the
After creating pin-related assignments, you must validate the assignments against
rules specific to the Cyclone III device. This section discusses the validation and
considerations about pin placement.
I/O Assignment Analysis
The Start I/O Assignment Analysis command allows you to check the legality of
your I/O assignments before, during, or after you compile your design. If design files
are available, you can use this command to perform thorough legality checks on your
design’s I/O pins and surrounding logic. These checks include proper reference
voltage pin usage, valid pin location assignments, and acceptable mixed I/O
standards. Run the analysis each time you add or modify a pin-related assignment.
For more information about the Start I/O Assignment Analysis command and its
design flow, refer to the
Handbook.
DC Guidelines
Sourcing or sinking large amounts of steady current from output pins can damage the
device due to electromigration, where the movement of the conducting metal's atoms
is caused by the large amount of electric current flowing through it. Some examples
pull a high output pin to ground or connect a low output pin to V
maximum DC current a Cyclone III I/O pin can sink is 25 mA and source is 40 mA. If
certain pins have to be pulled high or low, pull them through external resistors.
Tabular Text File (.ttf),
Raw Programming Data (.rpd) file, and
JTAG Indirect Configuration File (.jic).
Quartus II Programmer
I/O Management
Software Settings
chapter in volume 3 of the Quartus II Handbook.
chapter in volume 2 of the Quartus II
section in volume 2 of the
© November 2008 Altera Corporation
CC
Design and Compilation
directly. The