EP2C20F484C6N Altera, EP2C20F484C6N Datasheet - Page 65
![IC CYCLONE II FPGA 20K 484-FBGA](/photos/6/72/67258/544-484-fbga_sml.jpg)
EP2C20F484C6N
Manufacturer Part Number
EP2C20F484C6N
Description
IC CYCLONE II FPGA 20K 484-FBGA
Manufacturer
Altera
Series
Cyclone® IIr
Datasheet
1.EP2C5T144C8N.pdf
(168 pages)
Specifications of EP2C20F484C6N
Number Of Logic Elements/cells
18752
Number Of Labs/clbs
1172
Total Ram Bits
239616
Number Of I /o
315
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
Family Name
Cyclone® II
Number Of Logic Blocks/elements
18752
# I/os (max)
315
Frequency (max)
500MHz
Process Technology
90nm
Operating Supply Voltage (typ)
1.2V
Logic Cells
18752
Ram Bits
239616
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
484
Package Type
FBGA
For Use With
P0528 - BOARD DEV DE1 ALTERA544-1736 - CYCLONE II STARTER KIT EP2C20N
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-1670
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Altera Corporation
February 2007
Notes to
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
Differential HSTL-15 class I
or class II
Differential HSTL-18 class I
or class II
LVDS
RSDS and mini-LVDS
LVPECL
Table 2–17. Cyclone II Supported I/O Standards & Constraints (Part 2 of 2)
To drive inputs higher than V
LVTTL and LVCMOS input levels to overdrive input buffer option in the Quartus II software.
These pins support SSTL-18 class II and 1.8- and 1.5-V HSTL class II inputs.
PCI-X does not meet the IV curve requirement at the linear region. PCI-clamp diode is not available on top and
bottom I/O pins.
Pseudo-differential HSTL and SSTL outputs use two single-ended outputs with the second output programmed
as inverted. Pseudo-differential HSTL and SSTL inputs treat differential inputs as two single-ended HSTL and
SSTL inputs and only decode one of them.
This I/O standard is not supported on these I/O pins.
This I/O standard is only supported on the dedicated clock pins.
PLL_OUT does not support differential SSTL-18 class II and differential 1.8 and 1.5-V HSTL class II.
mini-LVDS and RSDS are only supported on output pins.
LVPECL is only supported on clock inputs.
I/O Standard
Table
(9)
2–17:
f
(8)
For more information on Cyclone II supported I/O standards, see the
Selectable I/O Standards in Cyclone II Devices chapter in Volume 1 of the
Cyclone II Device Handbook.
High-Speed Differential Interfaces
Cyclone II devices can transmit and receive data through LVDS signals at
a data rate of up to 640 Mbps and 805 Mbps, respectively. For the LVDS
transmitter and receiver, the Cyclone II device’s input and output pins
support serialization and deserialization through internal logic.
Pseudo
differential
Pseudo
differential
Differential
Differential
Differential
C C I O
Type
but less than 4.0 V, disable the PCI clamping diode and turn on the Allow
(4)
(4)
1.5 V
2.5 V
3.3 V/
2.5 V/
1.8 V/
1.5 V
Input Output
1.8 V
V
(5)
(5)
(5)
CCIO
Level
1.5 V
1.8 V
2.5 V
2.5 V
(5)
(5)
(5)
CLK,
DQS
Top & Bottom
v
v
v
v
(6)
(6)
I/O Pins
Cyclone II Device Handbook, Volume 1
User I/O
Pins
v
v
CLK,
DQS
v
(6)
v
(6)
v
v
Cyclone II Architecture
PLL_OUT
Side I/O Pins
v
v
v
v
(7)
(7)
User I/O
Pins
v
v
2–53