EP2C20F484C6N Altera, EP2C20F484C6N Datasheet - Page 75
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EP2C20F484C6N
Manufacturer Part Number
EP2C20F484C6N
Description
IC CYCLONE II FPGA 20K 484-FBGA
Manufacturer
Altera
Series
Cyclone® IIr
Datasheet
1.EP2C5T144C8N.pdf
(168 pages)
Specifications of EP2C20F484C6N
Number Of Logic Elements/cells
18752
Number Of Labs/clbs
1172
Total Ram Bits
239616
Number Of I /o
315
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
Family Name
Cyclone® II
Number Of Logic Blocks/elements
18752
# I/os (max)
315
Frequency (max)
500MHz
Process Technology
90nm
Operating Supply Voltage (typ)
1.2V
Logic Cells
18752
Ram Bits
239616
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
484
Package Type
FBGA
For Use With
P0528 - BOARD DEV DE1 ALTERA544-1736 - CYCLONE II STARTER KIT EP2C20N
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-1670
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
IEEE Std. 1149.1
(JTAG) Boundary
Scan Support
Altera Corporation
February 2007
CII51003-2.2
f
All Cyclone
the IEEE Std. 1149.1. JTAG boundary-scan testing can be performed
either before or after, but not during configuration. Cyclone II devices can
also use the JTAG port for configuration with the Quartus
hardware using either Jam Files (.jam) or Jam Byte-Code Files (.jbc).
Cyclone II devices support IOE I/O standard reconfiguration through the
JTAG BST chain. The JTAG chain can update the I/O standard for all
input and output pins any time before or during user mode through the
CONFIG_IO instruction. You can use this capability for JTAG testing
before configuration when some of the Cyclone II pins drive or receive
from other devices on the board using voltage-referenced standards.
Since the Cyclone II device might not be configured before JTAG testing,
the I/O pins may not be configured for appropriate electrical standards
for chip-to-chip communication. Programming the I/O standards via
JTAG allows you to fully test I/O connections to other devices.
For information on I/O reconfiguration, refer to the MorphIO: An I/O
Reconfiguration Solution for Altera Devices White Paper.
A device operating in JTAG mode uses four required pins: TDI, TDO, TMS,
and TCK. The TCK pin has an internal weak pull-down resister, while the
TDI and TMS pins have weak internal pull-up resistors. The TDO output
pin and all JTAG input pin voltage is determined by the V
where it resides. The bank V
1.8-, 2.5-, or 3.3-V compatible.
1
Stratix
within the first 8 devices in a JTAG chain. All of these devices
have the same JTAG controller. If any of the Stratix II, Stratix,
Cyclone II or Cyclone devices are in the 9th of further position,
they fail configuration. This does not affect Signal Tap II.
®
II devices provide JTAG BST circuitry that complies with
®
II, Stratix, Cyclone II and Cyclone devices must be
3. Configuration & Testing
CCIO
selects whether the JTAG inputs are 1.5-,
CCIO
®
II software or
of the bank
3–1