EP3C40F484C8N Altera, EP3C40F484C8N Datasheet - Page 18

• Manufacturer Part Number: EP3C40F484C8N
• Description: IC CYCLONE III FPGA 40K 484FBGA
• Manufacturer: Altera
• Series: Cyclone® IIIr

Specifications of EP3C40F484C8N

• Number Of Logic Elements/cells: 39600
• Number Of Labs/clbs: 2475
• Total Ram Bits: 1161216
• Number Of I /o: 331
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Cyclone III
• Number Of Logic Blocks/elements: 39600
• # I/os (max): 331
• Frequency (max): 402MHz
• Process Technology: 65nm
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 39600
• Ram Bits: 1161216
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FBGA
• No. Of Logic Blocks: 2475
• Family Type: Cyclone III
• No. Of I/o's: 331
• I/o Supply Voltage: 3.3V
• Operating Frequency Max: 402MHz
• Operating Temperature Range: 0°C To +85°C
• Rohs Compliant: Yes
• For Use With: 544-2601 - KIT DEV CYCLONE III LS EP3CLS200544-2411 - KIT DEV NIOS II CYCLONE III ED.
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-2492

Page 18
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f
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For details about implementing these features, refer to the
volume 2 of the Quartus II Handbook.
Minimizing Simultaneous Switching Noise
Simultaneous switching noise (SSN) becomes a concern when too many pins within
close proximity change levels at the same time and cause V
on the quiet pins nearby. Noise generated by SSN can reduce noise margin and cause
incorrect switching.
When creating your design, try to separate the pins that switch simultaneously. If
possible, distribute the switching pins to different I/O banks. Set the unused I/O pins
nearby to V
also turn on the slow slew rate feature and use a lower drive strength for the
switching pins. Proper termination on the switching I/O pins also helps to reduce
reflection and the SSN effect on the quiet pins.
For details about the sources of the SSN, ways to mitigate SSN and guidelines on a
PCB design for the general high speed digital designs, refer to
Simultaneous Switching Noise (SSN) Design Guidelines.
For board design guidelines, refer to
AN 315: Guidelines for Designing High-Speed FPGA PCBs.
Unused Pin Connection
The Quartus II software generates the pin report file (.pin) when you compile your
design. This report file specifies how you should connect the unused pins of your
device. For a Cyclone III device, unused I/O pins are marked in the report file as any
one of the following depending on how you set the unused pins in the Quartus II
software:
■
■
■
■
■
All I/O pins specified as GND* can either be connected to ground to improve the
device's immunity to noise, or left unconnected. Leave all RESERVE I/O pins
unconnected on your board because these I/O pins drive out unspecified signals.
Tying a RESERVED I/O pin to V
contention that can damage the output driver of the device.
RESERVED_INPUT I/O pins can be connected to a high or low signal on the board
while RESERVED_INPUT_WITH_WEAK_PULLUP and
RESERVED_INPUT_WITH_BUS_HOLD pins can be left unconnected.
GND*
RESERVED
RESERVED_INPUT
RESERVED_INPUT_WITH_WEAK_PULLUP
RESERVED_INPUT_WITH_BUS_HOLD
CC
to minimize V
CC
sag, or to ground to minimize ground bounce. You can
CC
, ground, or another signal source can create
AN 224: High-Speed Board Layout Guidelines
© November 2008 Altera Corporation
I/O Management
CC
sag or ground bounce
AN 508: Cyclone III
Board Design Considerations
chapter in
and