EP4CE40F29C7N Altera, EP4CE40F29C7N Datasheet - Page 281
![no-image](/images/manufacturer_photos/0/0/40/altera_sml.jpg)
EP4CE40F29C7N
Manufacturer Part Number
EP4CE40F29C7N
Description
IC CYCLONE IV E FPGA 40K 780FBGA
Manufacturer
Altera
Series
CYCLONE® IV Er
Datasheets
1.EP4CGX15BN11C8N.pdf
(44 pages)
2.EP4CGX15BN11C8N.pdf
(14 pages)
3.EP4CGX15BN11C8N.pdf
(478 pages)
4.EP4CGX15BN11C8N.pdf
(10 pages)
Specifications of EP4CE40F29C7N
Number Of Logic Elements/cells
39600
Number Of Labs/clbs
2475
Total Ram Bits
1134000
Number Of I /o
532
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
780-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Other names
544-2685
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP4CE40F29C7N
Manufacturer:
ALTERA
Quantity:
852
Part Number:
EP4CE40F29C7N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
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CYIV-52001-3.2
Table 1–1. Serial Protocols Supported by the Cyclone IV GX Transceiver Channels —Preliminary
© December 2010 Altera Corporation
PCI Express
Gbps Ethernet (GbE)
Common Public Radio Interface (CPRI)
OBSAI
XAUI
Serial digital interface (SDI)
Serial RapidIO
Serial Advanced Technology Attachment
(SATA)
V-by-one
Display Port
Notes to
(1) Provides the physical interface for PCI Express (PIPE)-compliant interface that supports Gen1 ×1, ×2, and ×4 initial lane width configurations.
(2) Supports data rates up to 2.5 Gbps only.
(3) Compliance to protocol specification is pending characterization.
When implementing ×1 or ×2 interface, remaining channels in the transceiver block are available to implement other protocols.
(3)
Table
(3)
®
(3)
f
(PCIe
1–1:
®
1
(SRIO)
Protocol
®
)
(1)
Cyclone
rates between 600 Mbps and 3.125 Gbps in a low-cost FPGA.
supported Cyclone IV GX transceiver channel serial protocols.
You can implement these protocols through the ALTGX MegaWizard™ Plug-In
Manager, which also offers the highly flexible Basic functional mode to implement
proprietary serial protocols at the following serial data rates:
■
■
For descriptions of the ports available when instantiating a transceiver using the
ALTGX megafunction, refer to
For more information about Cyclone IV transceivers that run at 2.97 Gbps data rate,
refer to the
The Cyclone IV GX device includes a hard intellectual property (IP) implementation
of the PCIe MegaCore
configured in the root port or endpoint mode. For more information, refer to
Express Hard IP Block” on page
600 Mbps to 2.5 Gbps for devices in F324 and smaller packages
600 Mbps to 3.125 Gbps for devices in F484 and larger packages
®
IV GX devices include up to eight full-duplex transceivers at serial data
Cyclone IV Device Family Pin Connection Guidelines.
0.6144, 1.2288, 2.4576, and 3.072
1. Cyclone IV Transceivers Architecture
®
HD-SDI at 1.485 and 1.4835
functions, supporting Gen1 ×1, ×2, and ×4 initial lane widths
3G-SDI at 2.97 and 2.967
0.768, 1.536, and 3.072
1.25, 2.5, and 3.125
Data Rate (Gbps)
1.62 and 2.7
1.5 and 3.0
“Transceiver Top-Level Port Lists” on page
1–42.
3.125
1.25
2.5
3.0
F324 and smaller
packages
Cyclone IV Device Handbook, Volume 2
v
v(2)
v
v
—
—
—
—
—
—
(2)
Table 1–1
F484 and larger
lists the
packages
1–79.
v
v
v
v
v
v
v
v
v
v
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