EP4CE40F29C7N Altera, EP4CE40F29C7N Datasheet - Page 288

• Manufacturer Part Number: EP4CE40F29C7N
• Description: IC CYCLONE IV E FPGA 40K 780FBGA
• Manufacturer: Altera
• Series: CYCLONE® IV Er

Specifications of EP4CE40F29C7N

• Number Of Logic Elements/cells: 39600
• Number Of Labs/clbs: 2475
• Total Ram Bits: 1134000
• Number Of I /o: 532
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2685

1–8
Serializer
Cyclone IV Device Handbook, Volume 2
Figure 1–10. Transmitter Bit Reversal Operation in Basic Single-Width Mode
■
■
The serializer converts the low-speed parallel 8-bit or 10-bit data from the transmitter
PCS to high-speed serial data for the transmitter output buffer. The serializer operates
with a high-speed clock at half of the serial data rate. The serializer transmission
sequence is LSB to MSB.
Input bit-flip—reverses the bit order at a byte level at the input of the transmitter
phase compensation FIFO. For example, if the 16-bit parallel transmitter data at
the tx_datain port is '10111100 10101101' (16'hBCAD), selecting this option
reverses the input data to the transmitter phase compensation FIFO to '00111101
10110101' (16'h3DB5).
Bit-slip control—delays the data transmission by a number of specified bits to the
serializer with the tx_bitslipboundaryselect port. For usage details, refer to
the
TX bit reversal option enabled in
the ALTGX MegaWizard
“Transmit Bit-Slip Control” on page
Output from transmitter PCS
D[9]
D[8]
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
1–70.
Chapter 1: Cyclone IV Transceivers Architecture
Converted data output to the
transmitter serializer
© December 2010 Altera Corporation
D[0]
D[1]
D[2]
D[3]
D[4]
D[5]
D[6]
D[7]
D[8]
D[9]
Transmitter Channel Datapath