EPF10K20RC208-3N Altera, EPF10K20RC208-3N Datasheet - Page 22

• Manufacturer Part Number: EPF10K20RC208-3N
• Description: IC FLEX 10K FPGA 20K 208-RQFP
• Manufacturer: Altera
• Series: FLEX-10K®r

Specifications of EPF10K20RC208-3N

• Number Of Logic Elements/cells: 1152
• Number Of Labs/clbs: 144
• Total Ram Bits: 12288
• Number Of I /o: 147
• Number Of Gates: 63000
• Voltage - Supply: 4.75 V ~ 5.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 208-RQFP
• Family Name: FLEX 10K
• Number Of Usable Gates: 20000
• Number Of Logic Blocks/elements: 1152
• # I/os (max): 147
• Frequency (max): 125MHz
• Process Technology: CMOS
• Operating Supply Voltage (typ): 5V
• Logic Cells: 1152
• Ram Bits: 12288
• Device System Gates: 63000
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 208
• Package Type: RQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2208

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FLEX 10K Embedded Programmable Logic Device Family Data Sheet
During compilation, the Compiler automatically selects the best control
signal implementation. Because the clear and preset functions are active-
low, the Compiler automatically assigns a logic high to an unused clear or
preset.
The clear and preset logic is implemented in one of the following six
modes chosen during design entry:
In addition to the six clear and preset modes, FLEX 10K devices provide a
chip-wide reset pin that can reset all registers in the device. Use of this
feature is set during design entry. In any of the clear and preset modes, the
chip-wide reset overrides all other signals. Registers with asynchronous
presets may be preset when the chip-wide reset is asserted. Inversion can
be used to implement the asynchronous preset.
of how to enter a section of a design for the desired functionality.
Asynchronous clear
Asynchronous preset
Asynchronous clear and preset
Asynchronous load with clear
Asynchronous load with preset
Asynchronous load without clear or preset
Figure 10
Altera Corporation
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