EPF10K30ETI144-2 Altera, EPF10K30ETI144-2 Datasheet - Page 13

IC FLEX 10KE FPGA 30K 144-TQFP

EPF10K30ETI144-2

Manufacturer Part Number
EPF10K30ETI144-2
Description
IC FLEX 10KE FPGA 30K 144-TQFP
Manufacturer
Altera
Series
FLEX-10KE®r
Datasheet

Specifications of EPF10K30ETI144-2

Number Of Logic Elements/cells
1728
Number Of Labs/clbs
216
Total Ram Bits
24576
Number Of I /o
102
Number Of Gates
119000
Voltage - Supply
2.375 V ~ 2.625 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
144-TQFP, 144-VQFP
Family Name
FLEX 10KE
Number Of Usable Gates
30000
Number Of Logic Blocks/elements
1728
# Registers
102
# I/os (max)
102
Frequency (max)
200MHz
Process Technology
CMOS
Operating Supply Voltage (typ)
2.5V
Logic Cells
1728
Ram Bits
24576
Device System Gates
119000
Operating Supply Voltage (min)
2.375V
Operating Supply Voltage (max)
2.625V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
144
Package Type
TQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
544-1944
EPF10K30ETI144-2

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EPF10K30ETI144-2
Manufacturer:
ALTERA
Quantity:
90
Part Number:
EPF10K30ETI144-2
Manufacturer:
Altera
Quantity:
10 000
Part Number:
EPF10K30ETI144-2
Manufacturer:
ALTERA
0
Part Number:
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Quantity:
20 000
Part Number:
EPF10K30ETI144-2N
Manufacturer:
ALTERA
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Altera Corporation
Figure 4. FLEX 10KE Device in Single-Port RAM Mode
Note:
(1)
EAB Local
Interconnect (1)
EPF10K30E, EPF10K50E, and EPF10K50S devices have 88 EAB local interconnect channels; EPF10K100E,
EPF10K130E, EPF10K200E, and EPF10K200S devices have 104 EAB local interconnect channels.
Dedicated
Clocks
2
Dedicated Inputs
& Global Signals
EABs can be used to implement synchronous RAM, which is easier to use
than asynchronous RAM. A circuit using asynchronous RAM must
generate the RAM write enable signal, while ensuring that its data and
address signals meet setup and hold time specifications relative to the
write enable signal. In contrast, the EAB’s synchronous RAM generates its
own write enable signal and is self-timed with respect to the input or write
clock. A circuit using the EAB’s self-timed RAM must only meet the setup
and hold time specifications of the global clock.
4
8, 9, 10, 11
8, 4, 2, 1
Chip-Wide
Reset
FLEX 10KE Embedded Programmable Logic Devices Data Sheet
D
D
D
Q
Q
Q
Row Interconnect
Data In
Address
Write Enable
RAM/ROM
1,024
2,048
Data Out
256
512
16
8
4
2
D
Q
4, 8, 16, 32
Column Interconnect
4, 8, 16, 32
4, 8
13

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