EPF10K30ETI144-2 Altera, EPF10K30ETI144-2 Datasheet - Page 31

IC FLEX 10KE FPGA 30K 144-TQFP

EPF10K30ETI144-2

Manufacturer Part Number
EPF10K30ETI144-2
Description
IC FLEX 10KE FPGA 30K 144-TQFP
Manufacturer
Altera
Series
FLEX-10KE®r
Datasheet

Specifications of EPF10K30ETI144-2

Number Of Logic Elements/cells
1728
Number Of Labs/clbs
216
Total Ram Bits
24576
Number Of I /o
102
Number Of Gates
119000
Voltage - Supply
2.375 V ~ 2.625 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
144-TQFP, 144-VQFP
Family Name
FLEX 10KE
Number Of Usable Gates
30000
Number Of Logic Blocks/elements
1728
# Registers
102
# I/os (max)
102
Frequency (max)
200MHz
Process Technology
CMOS
Operating Supply Voltage (typ)
2.5V
Logic Cells
1728
Ram Bits
24576
Device System Gates
119000
Operating Supply Voltage (min)
2.375V
Operating Supply Voltage (max)
2.625V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
144
Package Type
TQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
544-1944
EPF10K30ETI144-2

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EPF10K30ETI144-2
Manufacturer:
ALTERA
Quantity:
90
Part Number:
EPF10K30ETI144-2
Manufacturer:
Altera
Quantity:
10 000
Part Number:
EPF10K30ETI144-2
Manufacturer:
ALTERA
0
Part Number:
EPF10K30ETI144-2
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Part Number:
EPF10K30ETI144-2N
Manufacturer:
ALTERA
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Altera Corporation
Figure 15. FLEX 10KE Bidirectional I/O Registers
Note:
(1)
Row and Column
All FLEX 10KE devices (except the EPF10K50E and EPF10K200E devices) have a programmable input delay buffer
on the input path.
Interconnect
4 Dedicated
Inputs
4
Clock Inputs
2 Dedicated
2
Control Bus
Peripheral
12
CLK[3..2]
CLK[1..0]
OE[7..0]
VCC
ENA[5..0]
FLEX 10KE Embedded Programmable Logic Devices Data Sheet
VCC
VCC
VCC
CLRN[1..0]
VCC
Programmable Delay
VCC
Chip-Wide
Chip-Wide
Chip-Wide
(1)
Reset
Reset
Reset
Output Register (2)
Input Register (2)
OE Register
D
D
D
ENA
ENA
ENA
CLRN
CLRN
CLRN
Output Enable
Q
Q
Q
Chip-Wide
Open-Drain
Slew-Rate
Control
Output
31

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