EP2C35F484I8 Altera, EP2C35F484I8 Datasheet - Page 57
![IC CYCLONE II FPGA 33K 484-FBGA](/photos/6/72/67258/544-484-fbga_sml.jpg)
EP2C35F484I8
Manufacturer Part Number
EP2C35F484I8
Description
IC CYCLONE II FPGA 33K 484-FBGA
Manufacturer
Altera
Series
Cyclone® IIr
Datasheet
1.EP2C5T144C8N.pdf
(168 pages)
Specifications of EP2C35F484I8
Number Of Logic Elements/cells
33216
Number Of Labs/clbs
2076
Total Ram Bits
483840
Number Of I /o
322
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
484-FBGA
Family Name
Cyclone® II
Number Of Logic Blocks/elements
33216
# I/os (max)
322
Frequency (max)
402.58MHz
Process Technology
90nm
Operating Supply Voltage (typ)
1.2V
Logic Cells
33216
Ram Bits
483840
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
484
Package Type
FBGA
For Use With
P0301 - DE2 CALL FOR ACADEMIC PRICING544-1733 - PCI KIT W/CYCLONE II EP2C35N
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Not Compliant
Other names
544-2108
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP2C35F484I8
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Company:
Part Number:
EP2C35F484I8N
Manufacturer:
ALTERA
Quantity:
1 045
Part Number:
EP2C35F484I8N
Manufacturer:
ALTERA
Quantity:
20 000
Altera Corporation
February 2007
Notes to
(1)
(2)
(3)
(4)
SDR SDRAM
DDR SDRAM
DDR2 SDRAM
QDRII SRAM
Table 2–14. External Memory Support in Cyclone II Devices
Memory Standard
The data rate is for designs using the Clock Delay Control circuitry.
The I/O standards are supported on all the I/O banks of the Cyclone II device.
The I/O standards are supported only on the I/O banks on the top and bottom of the Cyclone II device.
For maximum performance, Altera recommends using the 1.8-V HSTL I/O standard because of higher I/O drive
strength. QDRII SRAM devices also support the 1.5-V HSTL I/O standard.
Table
(4)
2–14:
LVTTL
SSTL-2 class I
SSTL-2 class II
SSTL-18 class I
SSTL-18 class II
1.8-V HSTL class I
(2)
1.8-V HSTL class II
(3)
I/O Standard
In Cyclone II devices, all the I/O banks support SDR and DDR SDRAM
memory up to 167 MHz/333 Mbps. All I/O banks support DQS signals
with the DQ bus modes of ×8/×9, or ×16/×18.
external memory interfaces supported in Cyclone II devices.
Cyclone II devices use data (DQ), data strobe (DQS), and clock pins to
interface with external memory.
in the ×8/×9 mode.
(2)
(2)
(2)
(2)
(3)
Maximum Bus
Width
72
72
72
72
72
36
36
Figure 2–26
Note (1)
Cyclone II Device Handbook, Volume 1
Maximum Clock
Rate Supported
(MHz)
167
167
133
167
125
167
100
shows the DQ and DQS pins
Table 2–14
Cyclone II Architecture
Rate Supported
Maximum Data
shows the
(Mbps)
333
267
333
250
668
400
167
(1)
(1)
(1)
(1)
(1)
(1)
2–45