EPF10K30RC208-4 Altera, EPF10K30RC208-4 Datasheet - Page 23

• Manufacturer Part Number: EPF10K30RC208-4
• Description: IC FLEX 10K FPGA 30K 208-RQFP
• Manufacturer: Altera
• Series: FLEX-10K®r

Specifications of EPF10K30RC208-4

• Number Of Logic Elements/cells: 1728
• Number Of Labs/clbs: 216
• Total Ram Bits: 12288
• Number Of I /o: 147
• Number Of Gates: 69000
• Voltage - Supply: 4.75 V ~ 5.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 208-RQFP
• Family Name: FLEX 10K
• Number Of Usable Gates: 30000
• Number Of Logic Blocks/elements: 1728
• # Registers: 738
• # I/os (max): 147
• Frequency (max): 125MHz
• Process Technology: CMOS
• Operating Supply Voltage (typ): 5V
• Logic Cells: 1728
• Ram Bits: 12288
• Device System Gates: 69000
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 208
• Package Type: RQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 544-2229

Altera Corporation
Figure 10. LE Clear & Preset Modes
Chip-Wide Reset
Chip-Wide Reset
Asynchronous Clear
(Asynchronous
(Asynchronous
Asynchronous Load with Clear
Asynchronous Load with Preset
labctrl1 or
(Preset)
labctrl2
labctrl2
labctrl2
labctrl1
labctrl1
(Clear)
(Data)
(Data)
data3
data3
Load)
Load)
NOT
NOT
D
CLRN
VCC
PRN
NOT
NOT
Q
Asynchronous Clear
The flipflop can be cleared by either LABCTRL1 or LABCTRL2. In this
mode, the preset signal is tied to V
Chip-Wide Reset
FLEX 10K Embedded Programmable Logic Device Family Data Sheet
Chip-Wide Reset
Asynchronous Preset
labctrl1 or
labctrl2
D
CLRN
PRN
Q
VCC
D
CLRN
PRN
D
CLRN
PRN
(Asynchronous
Q
Asynchronous Load without Clear or Preset
Q
CC
labctrl1
(Data)
Load)
data3
to deactivate it.
Chip-Wide Reset
Chip-Wide Reset
NOT
NOT
Asynchronous Clear & Preset
labctrl1
labctrl2
D
CLRN
PRN
D
CLRN
PRN
Q
Q
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