EPF10K30RC208-4 Altera, EPF10K30RC208-4 Datasheet - Page 56
![IC FLEX 10K FPGA 30K 208-RQFP](/photos/6/70/67069/544-208-rqfp_sml.jpg)
EPF10K30RC208-4
Manufacturer Part Number
EPF10K30RC208-4
Description
IC FLEX 10K FPGA 30K 208-RQFP
Manufacturer
Altera
Series
FLEX-10K®r
Datasheet
1.EPF10K10ATC100-3.pdf
(128 pages)
Specifications of EPF10K30RC208-4
Number Of Logic Elements/cells
1728
Number Of Labs/clbs
216
Total Ram Bits
12288
Number Of I /o
147
Number Of Gates
69000
Voltage - Supply
4.75 V ~ 5.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
208-RQFP
Family Name
FLEX 10K
Number Of Usable Gates
30000
Number Of Logic Blocks/elements
1728
# Registers
738
# I/os (max)
147
Frequency (max)
125MHz
Process Technology
CMOS
Operating Supply Voltage (typ)
5V
Logic Cells
1728
Ram Bits
12288
Device System Gates
69000
Operating Supply Voltage (min)
4.75V
Operating Supply Voltage (max)
5.25V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
208
Package Type
RQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
544-2229
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EPF10K30RC208-4
Manufacturer:
ALTERA
Quantity:
5 530
Part Number:
EPF10K30RC208-4
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Company:
Part Number:
EPF10K30RC208-4N
Manufacturer:
ALTERA11
Quantity:
419
Part Number:
EPF10K30RC208-4N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Figure 24. FLEX 10K Device Timing Model
56
FLEX 10K Embedded Programmable Logic Device Family Data Sheet
Clock/Input
Dedicated
Timing simulation and delay prediction are available with the
MAX+PLUS II Simulator and Timing Analyzer, or with industry-
standard EDA tools. The Simulator offers both pre-synthesis functional
simulation to evaluate logic design accuracy and post-synthesis timing
simulation with 0.1-ns resolution. The Timing Analyzer provides point-
to-point timing delay information, setup and hold time analysis, and
device-wide performance analysis.
Figure 24
to and from the various elements of the FLEX 10K device.
shows the overall timing model, which maps the possible paths
Element
Logic
Interconnect
Embedded Array
Block
Altera Corporation
I/O Element