EP3C40F484C6N Altera, EP3C40F484C6N Datasheet - Page 48
![IC CYCLONE III FPGA 40K 484FBGA](/photos/6/72/67258/544-484-fbga_sml.jpg)
EP3C40F484C6N
Manufacturer Part Number
EP3C40F484C6N
Description
IC CYCLONE III FPGA 40K 484FBGA
Manufacturer
Altera
Series
Cyclone® IIIr
Datasheets
1.EP3C5F256C8N.pdf
(5 pages)
2.EP3C5F256C8N.pdf
(34 pages)
3.EP3C5F256C8N.pdf
(66 pages)
4.EP3C5F256C8N.pdf
(14 pages)
5.EP3C5F256C8N.pdf
(76 pages)
Specifications of EP3C40F484C6N
Number Of Logic Elements/cells
39600
Number Of Labs/clbs
2475
Total Ram Bits
1161216
Number Of I /o
331
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
For Use With
544-2601 - KIT DEV CYCLONE III LS EP3CLS200544-2411 - KIT DEV NIOS II CYCLONE III ED.
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Other names
544-2490
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP3C40F484C6N
Manufacturer:
ALTERA
Quantity:
1 400
Company:
Part Number:
EP3C40F484C6N
Manufacturer:
ALTERA44
Quantity:
377
Part Number:
EP3C40F484C6N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Page 48
Verification
I/O Timing Analysis
Perform I/O analysis with the TimeQuest Timing Analyzer or Classic Timing
Analyzer to ensure that the Cyclone III device meets the timing requirement when
interfacing with external devices on the board. If you know the maximum or
minimum delay of a signal from a register of an external device to a specified input or
bidirectional pin on the Cyclone III device relative to a specified clock source, use the
Input Delay assignment.
For the registered output from the Cyclone III device, you can make the Output Delay
assignment for maximum or minimum delay of a signal from the registered output of
the Cyclone III device to the registered input of the external device, relative to a
specified clock source.
Skew Management
Skew refers to the arrival time difference of a signal at two different destinations. For
synchronous designs, we have clock and data skew due to the different path length of
the clock and data signals. The effect of the skew is more significant on high speed
signals, due to the short time period of the signals. Using the clock network for these
high speed signals results in lower clock and data skew.
Use the Quartus II Maximum Clock Arrival Skew assignment to specify the
maximum allowable clock arrival skew between a clock signal and various
destination registers. For data signals, use the Maximum Data Arrival Skew
assignment to specify the maximum allowable data arrival skew to various
destination registers or pins. When these assignments are used, the Quartus II
software determines the timing difference between the longest clock or data path, and
the shortest clock or data path so that the Fitter attempts to meet the requirement.
Area and Timing Optimization
Physical synthesis optimizations make placement-specific changes to the netlist that
improve results for a specific Altera device. You can specify Physical synthesis for
performance or Physical synthesis for fitting options under the Fitter Settings, as in
Figure
9. These options typically increase compilation time significantly but can
provide significant improvements to the compilation result. If you turn on these
options, ensure that they do improve the results for your design.
© November 2008 Altera Corporation