EP3C40F484C6N Altera, EP3C40F484C6N Datasheet - Page 50
![IC CYCLONE III FPGA 40K 484FBGA](/photos/6/72/67258/544-484-fbga_sml.jpg)
EP3C40F484C6N
Manufacturer Part Number
EP3C40F484C6N
Description
IC CYCLONE III FPGA 40K 484FBGA
Manufacturer
Altera
Series
Cyclone® IIIr
Datasheets
1.EP3C5F256C8N.pdf
(5 pages)
2.EP3C5F256C8N.pdf
(34 pages)
3.EP3C5F256C8N.pdf
(66 pages)
4.EP3C5F256C8N.pdf
(14 pages)
5.EP3C5F256C8N.pdf
(76 pages)
Specifications of EP3C40F484C6N
Number Of Logic Elements/cells
39600
Number Of Labs/clbs
2475
Total Ram Bits
1161216
Number Of I /o
331
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
For Use With
544-2601 - KIT DEV CYCLONE III LS EP3CLS200544-2411 - KIT DEV NIOS II CYCLONE III ED.
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Other names
544-2490
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP3C40F484C6N
Manufacturer:
ALTERA
Quantity:
1 400
Company:
Part Number:
EP3C40F484C6N
Manufacturer:
ALTERA44
Quantity:
377
Part Number:
EP3C40F484C6N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Page 50
Figure 10. Design Space Explorer Window
f
f
For more information, refer to the
Quartus II Handbook.
The Optimization Advisors provide guidance in making settings that optimize your
design. On the Tools menu, point to Advisors, and click Resource Optimization
Advisor, or Timing Optimization Advisor. Evaluate the options and choose the
settings that best suit the requirements.
For more information about the various timing optimization settings in the Quartus II
software as well as the timing optimization techniques, refer to the
Integrated Synthesis
Timing Optimization
Recommended Timing Optimization and Analysis Assignments
The assignments and settings described in this section are not turned on in the
software by default for all designs, but are important for large designs.
Turn on Optimize fast-corner timing on the Fitter Settings page in the Settings
dialog box, as in
timing requirements at the Fast Timing process corner and operating condition, as
well as at the Slow Timing corner. Therefore, turning on this option helps create a
design implementation that is more robust across process, temperature, and voltage
variations.
Figure
chapter in volume 1 of the Quartus II Handbook and the
chapter in volume 2 of the Quartus II Handbook.
11. When this option is on, the design is optimized to meet its
Design Space Explorer
chapter in volume 2 of the
© November 2008 Altera Corporation
Quartus II
Area and
Verification