EP4CE55F29C8LN Altera, EP4CE55F29C8LN Datasheet - Page 306
EP4CE55F29C8LN
Manufacturer Part Number
EP4CE55F29C8LN
Description
IC CYCLONE IV FPGA 55K 780FBGA
Manufacturer
Altera
Series
CYCLONE® IV Er
Datasheets
1.EP4CGX15BN11C8N.pdf
(44 pages)
2.EP4CGX15BN11C8N.pdf
(14 pages)
3.EP4CGX15BN11C8N.pdf
(478 pages)
4.EP4CGX15BN11C8N.pdf
(10 pages)
Specifications of EP4CE55F29C8LN
Number Of Logic Elements/cells
55856
Number Of Labs/clbs
3491
Total Ram Bits
2340000
Number Of I /o
374
Voltage - Supply
0.97 V ~ 1.03 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
780-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
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1–26
Transceiver Channel Datapath Clocking
Cyclone IV Device Handbook, Volume 2
Figure 1–27
for REFCLK pins.
Figure 1–27. AC-Coupled Termination Scheme for a Reference Clock
Note to
(1) V
Figure 1–28
configured as a HCSL input.
Figure 1–28. Termination Scheme for a Reference Clock When Configured as HCSL
Notes to
(1) No biasing is required if the reference clock signals are generated from a clock source that conforms to the PCIe
(2) Select values as recommended by the PCIe clock source vendor.
Channel datapath clocking varies with channel configuration options and PCS
configurations. This section describes the clock distribution from the left PLLs for
transceiver channels and the datapath clocking in various supported configurations.
Table 1–7
Table 1–7. PLL Clocks for Transceiver Datapath
CDR clocks
High-speed clock
Low-speed clock
specification.
ICM
Figure
Figure
can be sourced from the 2.5-V supply with a voltage divider circuit (typically two 1-k resistors).
Clock
lists the clocks generated by the PLLs for transceiver datapath.
LVDS, LVPECL, PCML
(1.2 V, 1.5 V, 3.3 V)
1–27:
shows an example of the termination scheme for AC-coupled connections
shows an example termination scheme for the REFCLK pin when
1–28:
PCI Express
REFCLK
(HCSL)
Source
Receiver CDR unit
Transmitter serializer block in PMA
Transmitter PCS blocks
Receiver PCS blocks when rate match FIFO enabled
0.1 μF
0.1 μF
Z
Z
0
0
Rs
Rs
= 50 Ω
= 50 Ω
(2)
(2)
50 Ω
V
ICM
Chapter 1: Cyclone IV Transceivers Architecture
50 Ω
Usage
50 Ω
50 Ω
REFCLK
REFCLK
© December 2010 Altera Corporation
Cyclone IV GX
Transceiver Clocking Architecture
Cyclone IV GX
+
-
REFCLK
(Note 1)
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