EP4CGX110CF23I7N Altera, EP4CGX110CF23I7N Datasheet - Page 361
EP4CGX110CF23I7N
Manufacturer Part Number
EP4CGX110CF23I7N
Description
IC CYCLONE IV FPGA 110K 484FBGA
Manufacturer
Altera
Series
CYCLONE® IV GXr
Datasheets
1.EP4CGX15BN11C8N.pdf
(44 pages)
2.EP4CGX15BN11C8N.pdf
(14 pages)
3.EP4CGX15BN11C8N.pdf
(478 pages)
4.EP4CGX15BN11C8N.pdf
(10 pages)
Specifications of EP4CGX110CF23I7N
Number Of Logic Elements/cells
109424
Number Of Labs/clbs
6839
Total Ram Bits
5490000
Number Of I /o
270
Voltage - Supply
1.16 V ~ 1.24 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
484-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
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Chapter 1: Cyclone IV Transceivers Architecture
Transceiver Top-Level Port Lists
Table 1–27. Receiver Ports in ALTGX Megafunction for Cyclone IV GX (Part 2 of 3)
© December 2010 Altera Corporation
RX PCS
Block
rx_rmfifofull
rx_rmfifoempty
rx_ctrldetect
rx_errdetect
rx_disperr
rx_runningdisp
rx_enabyteord
rx_byteorder
alignstatus
rx_dataout
rx_clkout
Port Name
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output Clock signal
Input/
Input
Synchronous to tx_clkout (non-
bonded modes) or coreclkout
(bonded modes)
Synchronous to tx_clkout (non-
bonded modes) or coreclkout
(bonded modes)
Synchronous to tx_clkout (non-
bonded modes) or coreclkout
(bonded modes)
Synchronous to tx_clkout (non-
bonded modes) or coreclkout
(bonded modes)
Synchronous to tx_clkout (non-
bonded modes) or coreclkout
(bonded modes)
Synchronous to tx_clkout (non-
bonded modes) or coreclkout
(bonded modes)
Asynchronous signal
Synchronous to tx_clkout (non-
bonded modes) or coreclkout
(bonded modes)
Synchronous to tx_clkout (non-
bonded modes) or coreclkout
(bonded modes)
Clock Domain
Rate match FIFO full status indicator.
■
■
Rate match FIFO empty status indicator.
■
■
8B/10B decoder control or data identifier.
■
■
8B/10B code group violation or disparity error indicator.
■
■
8B/10B disparity error indicator.
■
8B/10B current running disparity indicator.
■
■
Enable byte ordering control
■
Byte ordering status indicator.
■
Parallel data output from the receiver to the FPGA fabric.
■
FPGA fabric-receiver interface clock when rate match FIFO
is not used.
A high level indicates the rate match FIFO is full.
Driven for a minimum of two serial clock cycles in
configurations without a byte serializer and a minimum
of three recovered clock cycles in configurations with a
byte serializer.
A high level indicates the rate match FIFO is empty.
Driven for a minimum of two serial clock cycles in
configurations without a byte serializer and a minimum
of three recovered clock cycles in configurations with a
byte serializer.
A high level indicates received code group is a /Kx.y/
control code group.
A low level indicates received code group is a /Dx.y/ data
code group.
A high level indicates that a code group violation or
disparity error was detected on the associated received
code group.
Use with the rx_disperr signal to differentiate
between a code group violation or a disparity error as
follows:[rx_errdetect:rx_disperr]
A high level indicates that a disparity error was detected
on the associated received code group.
A high level indicates a positive current running disparity
at the end of the decoded byte
A low level indicates a negative current running disparity
at the end of the decoded byte
A low-to-high transition triggers the byte ordering block
to restart byte ordering operation.
A high level indicates that the byte ordering block has
detected the programmed byte ordering pattern in the
least significant byte of the received data from the byte
deserializer.
Bus width depends on channel width multiplied by
number of channels per instance.
2'b00—no error
2'b10—code group violation
2'b11—disparity error or both
Cyclone IV Device Handbook, Volume 2
Description
1–81
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