EP1SGX10CF672C7N Altera, EP1SGX10CF672C7N Datasheet - Page 244
![IC STRATIX GX FPGA 10KLE 672FBGA](/photos/6/72/67292/544-672-fbga_sml.jpg)
EP1SGX10CF672C7N
Manufacturer Part Number
EP1SGX10CF672C7N
Description
IC STRATIX GX FPGA 10KLE 672FBGA
Manufacturer
Altera
Series
Stratix® GXr
Datasheet
1.EP1SGX10CF672C7N.pdf
(272 pages)
Specifications of EP1SGX10CF672C7N
Number Of Logic Elements/cells
10570
Number Of Labs/clbs
1057
Total Ram Bits
920448
Number Of I /o
362
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
672-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
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Timing Model
6–42
Stratix GX Device Handbook, Volume 1
t
t
t
t
t
t
t
t
t
t
t
t
t
OUTCO
INSUPLL
INHPLL
OUTCOPLL
INSU
INH
OUTCO
INSU
INH
OUTCO
INSUPLL
INHPLL
OUTCOPLL
Table 6–65. EP1SGX25 Row Pin Global Clock External I/O Timing Parameters (Part 2 of 2)
Table 6–66. EP1SGX40 Column Pin Fast Regional Clock External I/O Timing Parameters
Table 6–67. EP1SGX40 Column Pin Regional Clock External I/O Timing Parameters
Symbol
Symbol
Symbol
2.000
1.326
0.000
0.500
2.704
0.000
2.000
2.467
0.000
2.000
1.254
0.000
0.500
Min
Min
Min
-5 Speed Grade
-5 Speed Grade
-5 Speed Grade
Tables 6–66
and row pins for EP1SGX40 devices.
5.060
4.887
2.304
5.255
2.610
Max
Max
Max
through
2.000
1.386
0.000
0.500
2.912
0.000
2.000
2.671
0.000
2.000
1.259
0.000
0.500
Min
Min
Min
-6 Speed Grade
-6 Speed Grade
-6 Speed Grade
6–71
show the external timing parameters on column
5.432
5.247
2.427
5.673
2.751
Max
Max
Max
2.000
1.552
0.000
0.500
3.235
0.000
2.000
3.011
0.000
2.000
1.445
0.000
0.500
Min
Min
Min
-7 Speed Grade
-7 Speed Grade
-7 Speed Grade
6.226
6.011
2.765
6.501
3.134
Max
Max
Max
Altera Corporation
June 2006
Unit
Unit
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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