EP1SGX10CF672C7N Altera, EP1SGX10CF672C7N Datasheet - Page 35
![IC STRATIX GX FPGA 10KLE 672FBGA](/photos/6/72/67292/544-672-fbga_sml.jpg)
EP1SGX10CF672C7N
Manufacturer Part Number
EP1SGX10CF672C7N
Description
IC STRATIX GX FPGA 10KLE 672FBGA
Manufacturer
Altera
Series
Stratix® GXr
Datasheet
1.EP1SGX10CF672C7N.pdf
(272 pages)
Specifications of EP1SGX10CF672C7N
Number Of Logic Elements/cells
10570
Number Of Labs/clbs
1057
Total Ram Bits
920448
Number Of I /o
362
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
672-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- Current page: 35 of 272
- Download datasheet (3Mb)
Altera Corporation
June 2006
Table 2–8. Code Conversion
XGMII RXC
0
1
1
1
1
1
1
1
1
00 through FF
07
07
9C
FB
FD
FE
FE
See IEEE 802.3 reserved code
groups
XGMII RXD
Receiver State Machine
The receiver state machine operates in GIGE and XAUI modes. In GIGE
mode, the receiver state machine replaces invalid code groups with
9’h1FE. In XAUI mode, the receiver state machine translates the XAUI
PCS code group to the XAUI XGMII code group.
code conversion. The conversion adheres to the IEEE 802.3ae
specification.
Byte Deserializer
The byte deserializer takes a single width word (8 or 10 bits) from the
transceiver logic and converts it into double-width words (16 or 20 bits)
to the phase compensation FIFO buffer. The byte deserializer is bypassed
when single width mode (8 or 10 bits) is used at the PLD interface.
Phase Compensation FIFO Buffer
The receiver phase compensation FIFO buffer resides in the transceiver
block at the programmable logic device (PLD) boundary. This buffer
compensates for the phase difference between the recovered clock within
the transceiver and the recovered clock after it has transferred to the PLD
core. The phase compensation FIFO buffer is four words deep and cannot
be bypassed.
Dxx.y
K28.0 or K28.3 or K28.5
K28.5
K28.4
K27.7
K29.7
K30.7
Invalid code group
See IEEE 802.3 reserved
code groups
PCS code-group
Stratix GX Device Handbook, Volume 1
Normal Data
Idle in ||I||
Idle in ||T||
Sequence
Start
Terminate
Error
Invalid XGMII character
Reserved code groups
Table 2–8
Stratix GX Transceivers
Description
shows the
2–25
Related parts for EP1SGX10CF672C7N
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
![DK-CYCII-2C20N](/photos/9/20/92074/mfgdk-cycii-2c20nboard_tmb.jpg)
Part Number:
Description:
CYCLONE II STARTER KIT EP2C20N
Manufacturer:
Altera
Datasheet:
![EP610PC-35](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 35 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
![EP610PC-15](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 15 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
![EP610IPC-25](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
![EP610PC-30](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 30 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
![EP220PC-10](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 10ns
Manufacturer:
Altera Corporation
Datasheet:
![EP220PC-7](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 7ns
Manufacturer:
Altera Corporation
Datasheet:
![EP220PC-12](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
Classic EPLD
Manufacturer:
Altera Corporation
Datasheet:
![EP220PC-10A](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 10ns
Manufacturer:
Altera Corporation
Datasheet:
![P85C224-66](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
![EP320PC](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
![EP2A15B724C7](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
![EP610PC-25T](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 25 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet: