EP2S15F672I4N Altera, EP2S15F672I4N Datasheet - Page 15
EP2S15F672I4N
Manufacturer Part Number
EP2S15F672I4N
Description
IC STRATIX II FPGA 15K 672-FBGA
Manufacturer
Altera
Series
Stratix® IIr
Datasheet
1.EP2S15F484I4N.pdf
(238 pages)
Specifications of EP2S15F672I4N
Number Of Logic Elements/cells
15600
Number Of Labs/clbs
780
Total Ram Bits
419328
Number Of I /o
366
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
672-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Available stocks
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Manufacturer
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Part Number:
EP2S15F672I4N
Manufacturer:
ALTERA
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Figure 2–5. High-Level Block Diagram of the Stratix II ALM
Altera Corporation
May 2007
datae0
datae1
dataf0
dataf1
dataa
datab
datad
datac
Combinational
Logic
completely backward-compatible with four-input LUT architectures. One
ALM can also implement any function of up to six inputs and certain
seven-input functions.
In addition to the adaptive LUT-based resources, each ALM contains two
programmable registers, two dedicated full adders, a carry chain, a
shared arithmetic chain, and a register chain. Through these dedicated
resources, the ALM can efficiently implement various arithmetic
functions and shift registers. Each ALM drives all types of interconnects:
local, row, column, carry chain, shared arithmetic chain, register chain,
and direct link interconnects.
diagram of the Stratix II ALM while
all the connections in the ALM.
shared_arith_out
shared_arith_in
carry_out
carry_in
adder0
adder1
reg_chain_out
reg_chain_in
Figure 2–5
Figure 2–6
Stratix II Device Handbook, Volume 1
shows a high-level block
D
D
reg0
reg1
Q
Q
shows a detailed view of
Stratix II Architecture
To general or
To general or
To general or
To general or
local routing
local routing
local routing
local routing
2–7
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