EP2C70F896C6N Altera, EP2C70F896C6N Datasheet - Page 54
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EP2C70F896C6N
Manufacturer Part Number
EP2C70F896C6N
Description
IC CYCLONE II FPGA 70K 896-FBGA
Manufacturer
Altera
Series
Cyclone® IIr
Datasheet
1.EP2C5T144C8N.pdf
(168 pages)
Specifications of EP2C70F896C6N
Number Of Logic Elements/cells
68416
Number Of Labs/clbs
4276
Total Ram Bits
1152000
Number Of I /o
622
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
896-FBGA
For Use With
P0304 - DE2-70 CALL FOR ACADEMIC PRICING544-1703 - VIDEO KIT W/CYCLONE II EP2C70N544-1699 - DSP KIT W/CYCLONE II EPS2C70N
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Other names
544-2145
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP2C70F896C6N
Manufacturer:
ALTERA
Quantity:
4
Part Number:
EP2C70F896C6N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
I/O Structure & Features
Figure 2–24. Control Signal Selection per IOE
2–42
Cyclone II Device Handbook, Volume 1
Dedicated I/O
Clock [5..0]
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
io_coe
io_csclr
io_caclr
io_cce_out
io_cce_in
io_cclk
In normal bidirectional operation, you can use the input register for input
data requiring fast setup times. The input register can have its own clock
input and clock enable separate from the OE and output registers. You can
use the output register for data requiring fast clock-to-output
performance. The OE register is available for fast clock-to-output enable
timing. The OE and output register share the same clock source and the
same clock enable source from the local interconnect in the associated
LAB, dedicated I/O clocks, or the column and row interconnects. All
registers share sclr and aclr, but each register can individually disable
sclr and aclr.
configuration.
clk_in
Figure 2–25
clk_out
shows the IOE in bidirectional
ce_in
ce_out
aclr/preset
Altera Corporation
sclr/preset
February 2007
oe