EP3CLS70F484I7N Altera, EP3CLS70F484I7N Datasheet - Page 14
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EP3CLS70F484I7N
Manufacturer Part Number
EP3CLS70F484I7N
Description
IC FPGA CYCIII LS 70K 484-FBGA
Manufacturer
Altera
Series
Cyclone® IIIr
Datasheets
1.EP3C5F256C8N.pdf
(5 pages)
2.EP3C5F256C8N.pdf
(34 pages)
3.EP3C5F256C8N.pdf
(66 pages)
4.EP3C5F256C8N.pdf
(14 pages)
5.EP3C5F256C8N.pdf
(76 pages)
6.EP3CLS70F484I7N.pdf
(274 pages)
Specifications of EP3CLS70F484I7N
Number Of Logic Elements/cells
70208
Number Of Labs/clbs
4388
Total Ram Bits
3068928
Number Of I /o
278
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
484-FBGA
Family Name
Cyclone III LS
Number Of Logic Blocks/elements
70208
# I/os (max)
278
Frequency (max)
437.5MHz
Process Technology
65nm
Operating Supply Voltage (typ)
1.2V
Logic Cells
70208
Ram Bits
3068928
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
484
Package Type
FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
1–14
Table 1–18. Cyclone III Devices Differential I/O Standard Specifications
Power Consumption
Cyclone III Device Handbook, Volume 2
mini-LVDS
(Row I/Os)
(6)
mini-LVDS
(Column
I/Os)
RSDS
(Row
I/Os)(6)
RSDS
(Column
I/Os)
PPDS
(Row I/Os)
(6)
PPDS
(Column
I/Os)
Notes to
(1) For an explanation of terms used in
(2) V
(3) R
(4) LVPECL input standard is only supported at clock input. Output standard is not supported.
(5) No fixed V
(6) Mini-LVDS, RSDS, and PPDS standards are only supported at the output pins for Cyclone III devices.
Standard
I/O
IN
(6)
(6)
(6)
L
®
®
range: 90 ≤ R
range: 0 V ≤ V
Table
IN
f
1–18:
, V
2.375
2.375
2.375
2.375
2.375
2.375
Min
OD
L
, and V
IN
≤ 110 Ω.
≤ 1.85 V.
V
C CIO
You can use the following methods to estimate power for a design:
■
■
The interactive Excel-based EPE is used prior to designing the device to get a
magnitude estimate of the device power. The Quartus II PowerPlay power analyzer
provides better quality estimates based on the specifics of the design after place-and-
route is complete. The PowerPlay power analyzer can apply a combination of user-
entered, simulation-derived, and estimated signal activities which, combined with
detailed circuit models, can yield very accurate power estimates.
For more information about power estimation tools, refer to the
User Guide
Handbook.
Typ
2.5
2.5
2.5
2.5
2.5
2.5
OS
(V)
specifications for BLVDS. They are dependent on the system topology.
the Excel-based EPE.
the Quartus II PowerPlay power analyzer feature.
2.625
2.625
2.625
2.625
2.625
2.625
Max
Table
and the
Min
—
—
—
—
—
—
1–18, refer to
V
ID
(mV)
Max
PowerPlay Power Analysis
—
—
—
—
—
—
“Transmitter Output Waveform”
Min
—
—
—
—
—
—
V
Condition
IcM
(V)
—
—
—
—
—
—
(2)
(Note 1)
chapter in volume 3 of the Quartus II
in
Max Min Typ
“Glossary” on page
—
—
—
—
—
—
(Part 2 of 2)
300
300
100 200
100 200
100 200
100 200
Chapter 1: Cyclone III Device Data Sheet
V
O D
© January 2010 Altera Corporation
(mV)
—
—
1–27.
Early Power Estimator
(3)
Max
600
600
600
600
600
600
Electrical Characteristics
Min
1.0
1.0
0.5
0.5
0.5
0.5
V
O S
Typ
(V)
1.2
1.2
1.2
1.2
1.2
1.2
(3)
Max
1.4
1.4
1.5
1.5
1.4
1.4