EP1S20F780C7 Altera, EP1S20F780C7 Datasheet - Page 126
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EP1S20F780C7
Manufacturer Part Number
EP1S20F780C7
Description
IC STRATIX FPGA 20K LE 780-FBGA
Manufacturer
Altera
Series
Stratix®r
Datasheet
1.EP1S10F780C7.pdf
(276 pages)
Specifications of EP1S20F780C7
Number Of Logic Elements/cells
18460
Number Of Labs/clbs
1846
Total Ram Bits
1669248
Number Of I /o
586
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
780-FBGA
Family Name
Stratix
Number Of Logic Blocks/elements
18460
# I/os (max)
586
Frequency (max)
420.17MHz
Process Technology
0.13um (CMOS)
Operating Supply Voltage (typ)
1.5V
Logic Cells
18460
Ram Bits
1669248
Operating Supply Voltage (min)
1.425V
Operating Supply Voltage (max)
1.575V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Not Compliant
Other names
544-1116
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1S20F780C7
Manufacturer:
ALTERA
Quantity:
1 238
Company:
Part Number:
EP1S20F780C7
Manufacturer:
ALTERA
Quantity:
453
Company:
Part Number:
EP1S20F780C7L
Manufacturer:
NXP
Quantity:
1 448
Company:
Part Number:
EP1S20F780C7N
Manufacturer:
ALTERA
Quantity:
3 000
I/O Structure
Figure 2–65. Stratix IOE in DDR Input I/O Configuration
Notes to
(1)
(2)
(3)
2–112
Stratix Device Handbook, Volume 1
Column or Row
Interconnect
All input signals to the IOE can be inverted at the IOE.
This signal connection is only allowed on dedicated DQ function pins.
This signal is for dedicated DQS function pins only.
I/O Interconnect
Figure
[15..0]
2–65:
ioe_clk[7..0]
(1)
DQS Local
Bus (1), (2)
(1)
sclr
clkin
aclr/prn
Chip-Wide Reset
Enable Delay
Output Clock
Input Register
Input Register
Note (1)
D
ENA
CLRN/PRN
D
CLRN/PRN
ENA
Input Register Delay
Input Pin to
Q
Q
D
ENA
CLRN/PRN
To DQS Local
Latch
Bus (3)
Q
VCCIO
Altera Corporation
VCCIO
Optional
PCI Clamp
Bus-Hold
Circuit
July 2005
Programmable
Pull-Up
Resistor