EP1S20F672I7N Altera, EP1S20F672I7N Datasheet - Page 120
![IC STRATIX FPGA 20K LE 672-FBGA](/photos/6/73/67394/ds-672fbga205-2_0_sml.jpg)
EP1S20F672I7N
Manufacturer Part Number
EP1S20F672I7N
Description
IC STRATIX FPGA 20K LE 672-FBGA
Manufacturer
Altera
Series
Stratix®r
Datasheet
1.EP1S10F780C7.pdf
(276 pages)
Specifications of EP1S20F672I7N
Number Of Logic Elements/cells
18460
Number Of Labs/clbs
1846
Total Ram Bits
1669248
Number Of I /o
426
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
672-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1S20F672I7N
Manufacturer:
ALTERA20
Quantity:
212
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I/O Structure
Figure 2–60. Row I/O Block Connection to the Interconnect
Notes to
(1)
(2)
2–106
Stratix Device Handbook, Volume 1
Interconnect
LAB Local
The 16 control signals are composed of four output enables io_boe[3..0], four clock enables io_bce[3..0],
four clocks io_clk[3..0], and four clear signals io_bclr[3..0].
The 28 data and control signals consist of eight data out lines: four lines each for DDR applications
io_dataouta[3..0] and io_dataoutb[3..0], four output enables io_coe[3..0], four input clock enables
io_cce_in[3..0], four output clock enables io_cce_out[3..0], four clocks io_cclk[3..0], and four clear
signals io_cclr[3..0].
Figure
R4, R8 & R24
Interconnects
to Adjacent LAB
Interconnect
Direct Link
2–60:
LAB
io_dataouta[3..0]
io_dataoutb[3..0]
C4, C8 & C16
Interconnects
to Adjacent LAB
Interconnect
Direct Link
I/O Block Local
Interconnect
I/O Interconnect
io_clk[7:0]
16
28
from I/O Interconnect (1)
16 Control Signals
Horizontal
I/O Block
up to Four IOEs
Block Contains
Horizontal I/O
Altera Corporation
28 Data & Control
Signals from
Logic Array (2)
July 2005
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