EP2AGX65DF29C6N Altera, EP2AGX65DF29C6N Datasheet - Page 90

• Manufacturer Part Number: EP2AGX65DF29C6N
• Description: IC ARRIA II GX FPGA 65K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX65DF29C6N

• Number Of Logic Elements/cells: 60214
• Number Of Labs/clbs: 2530
• Total Ram Bits: 5246
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 63250
• # I/os (max): 364
• Frequency (max): 400MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 63250
• Ram Bits: 5557452.8
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

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Document Revision History
Table 1–68. Document Revision History (Part 1 of 2)
Arria II Device Handbook Volume 3: Device Datasheet and Addendum
December 2010
July 2010
March 2010
February 2010
February 2010
November 2009
Date
Version
Table 1–68
4.0
2.0
3.0
2.3
2.2
2.1
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Updated for the Quartus II version 9.1 SP2 release:
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Updated Table 1–19.
Updated for Arria II GX v9.1 SP1 release:
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Updated for Arria II GX v9.1 release:
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Added Arria II GZ information.
Added
Updated
Table
Table
Updated
Updated for the Quartus II version 10.0 release.
Updated the first paragraph for searchability.
Minor text edits.
Updated Table 1–1, Table 1–4, Table 1–16, Table 1–19, Table 1–21, Table 1–23,
Table 1–25, Table 1–26, Table 1–30, and Table 1–35
Added Table 1–27 and Table 1–29.
Added I3 speed grade information to Table 1–19, Table 1–21, Table 1–22, Table 1–24,
Table 1–25, Table 1–30, Table 1–32, Table 1–33, Table 1–34, and Table 1–35.
Updated the “Operating Conditions” section.
Removed “Preliminary” from Table 1–19, Table 1–21, Table 1–22, Table 1–23,
Table 1–24, Table 1–25, Table 1–26, Table 1–28, Table 1–30, Table 1–32, Table 1–33,
Table 1–34, and Figure 1–4.
Minor text edits.
Updated Table 1–3, Table 1–7, Table 1–19, Table 1–21, Table 1–22, Table 1–24,
Table 1–25 and Table 1–33.
Updated “Recommended Operating Conditions” section.
Minor text edits.
Updated Table 1–19, Table 1–23, Table 1–28, Table 1–30, and Table 1–33.
Added Figure 1–5.
Minor text edits.
Updated Table 1–1, Table 1–4, Table 1–13, Table 1–14, Table 1–19, Table 1–15,
Table 1–22, Table 1–24, and Table 1–28.
Added Table 1–6 and Table 1–33.
Added “Bus Hold” on page 1–5.
Added “IOE Programmable Delay” section.
Minor text edit.
lists the revision history for this chapter.
1–37,
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Table 1–61
Table
Figure
Table
1–1,
1–5.
1–40,
with Arria II GX information.
Table
Table
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1–42,
Table
1–5,
Table
Changes
Table
1–44,
Chapter 1: Device Datasheet for Arria II Devices
1–6,
Table
Table
1–45,
1–7,
December 2010 Altera Corporation
Table
Table
1–57,
Document Revision History
1–11,
Table
Table
1–61, and
1–35,