EP1SGX10DF672I6 Altera, EP1SGX10DF672I6 Datasheet - Page 28

IC STRATIX GX FPGA 10KLE 672FBGA

EP1SGX10DF672I6

Manufacturer Part Number
EP1SGX10DF672I6
Description
IC STRATIX GX FPGA 10KLE 672FBGA
Manufacturer
Altera
Series
Stratix® GXr
Datasheet

Specifications of EP1SGX10DF672I6

Number Of Logic Elements/cells
10570
Number Of Labs/clbs
1057
Total Ram Bits
920448
Number Of I /o
362
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
672-FBGA
Family Name
Stratix GX
Number Of Logic Blocks/elements
10570
# I/os (max)
362
Frequency (max)
5GHz
Process Technology
SRAM
Operating Supply Voltage (typ)
1.5V
Logic Cells
10570
Ram Bits
920448
Operating Supply Voltage (min)
1.425V
Operating Supply Voltage (max)
1.575V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
672
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Not Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP1SGX10DF672I6
Manufacturer:
Altera
Quantity:
10 000
Part Number:
EP1SGX10DF672I6
Manufacturer:
ALTERA
0
Part Number:
EP1SGX10DF672I6L
Manufacturer:
ALTERA
0
Part Number:
EP1SGX10DF672I6N
Manufacturer:
Altera
Quantity:
10 000
Part Number:
EP1SGX10DF672I6N
Manufacturer:
XILINX
0
2–18
Stratix GX Device Handbook, Volume 1
Deserializer (Serial-to-Parallel Converter)
The deserializer converts the serial stream into a parallel 8- or 10-bit data
bus. The deserializer receives the least significant bit first.
a diagram of the deserializer.
Figure 2–14. Deserializer
Word Aligner
The word aligner aligns the incoming data based on the specific byte
boundaries. The word aligner has three customizable modes of operation:
bit-slip mode, 16-bit mode, and 10-bit mode, the last of which is available
for the basic and SONET modes. The word aligner also has two
non-customizable modes of operation, which are the XAUI and GIGE
modes.
Figure 2–15
parallel clock
High-speed
serial clock
Low-speed
shows the word aligner in bit-slip mode.
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
D8
D9
Altera Corporation
Figure 2–14
10
June 2006
is

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