EP1SGX25FF1020C7 Altera, EP1SGX25FF1020C7 Datasheet - Page 99
![no-image](/images/manufacturer_photos/0/0/40/altera_sml.jpg)
EP1SGX25FF1020C7
Manufacturer Part Number
EP1SGX25FF1020C7
Description
IC STRATIX GX FPGA 25K 1020-FBGA
Manufacturer
Altera
Series
Stratix® GXr
Datasheet
1.EP1SGX10CF672C7N.pdf
(272 pages)
Specifications of EP1SGX25FF1020C7
Number Of Logic Elements/cells
25660
Number Of Labs/clbs
2566
Total Ram Bits
1944576
Number Of I /o
607
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1020-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1SGX25FF1020C7ES
Manufacturer:
ALTERA
Quantity:
11
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Figure 4–18. M-RAM Block Control Signals
Altera Corporation
February 2005
Dedicated
Row LAB
Clocks
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
One of the M-RAM block’s horizontal sides drive the address and control
signal (clock, renwe, byteena, etc.) inputs. Typically, the horizontal side
closest to the device perimeter contains the interfaces. The one exception
is when two M-RAM blocks are paired next to each other. In this case, the
side of the M-RAM block opposite the common side of the two blocks
contains the input interface. The top and bottom sides of any M-RAM
block contain data input and output interfaces to the logic array. The top
side has 72 data inputs and 72 data outputs for port B, and the bottom side
has another 72 data inputs and 72 data outputs for port A.
shows an example floorplan for the EP1SGX40 device and the location of
the M-RAM interfaces.
8
clock_a
clocken_a
clock_b
clocken_b
Stratix GX Device Handbook, Volume 1
aclr_a
aclr_b
Stratix GX Architecture
renwe_a
Figure 4–19
renwe_b
4–33
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