EP1S25F1020C5 Altera, EP1S25F1020C5 Datasheet - Page 62

no-image

EP1S25F1020C5

Manufacturer Part Number
EP1S25F1020C5
Description
IC STRATIX FPGA 25K LE 1020-FBGA
Manufacturer
Altera
Series
Stratix®r
Datasheet

Specifications of EP1S25F1020C5

Number Of Logic Elements/cells
25660
Number Of Labs/clbs
2566
Total Ram Bits
1944576
Number Of I /o
706
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1020-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Other names
544-1857
EP1S25F1020C5

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP1S25F1020C5
Manufacturer:
Altera
Quantity:
10 000
Part Number:
EP1S25F1020C5
Manufacturer:
ALTERA
0
Part Number:
EP1S25F1020C5
Manufacturer:
ALTERA
Quantity:
5
Part Number:
EP1S25F1020C5N
Manufacturer:
Altera
Quantity:
10 000
Part Number:
EP1S25F1020C5N
Manufacturer:
ALTERA
0
Part Number:
EP1S25F1020C5N
Manufacturer:
ALTERA
Quantity:
20 000
TriMatrix Memory
Figure 2–26. Input/Output Clock Mode in Simple Dual-Port Mode
Notes to
(1)
(2)
2–48
Stratix Device Handbook, Volume 1
wraddress[ ]
address[ ]
byteena[ ]
outclken
wrclock
inclken
rdclock
data[ ]
All registers shown except the rden register have asynchronous clear ports.
Violating the setup or hold time on the address registers could corrupt the memory contents. This applies to both
read and write operations.
wren
rden
Figure
8 LAB Row
Clocks
8
2–26:
D
ENA
D
ENA
D
ENA
D
ENA
D
ENA
D
ENA
Q
Q
Q
Q
Q
Q
Generator
Pulse
Write
Data In
Read Address
Byte Enable
Write Address
Read Enable
Write Enable
Notes
Memory Block
Data Out
1,024 ´ 4
2,048 ´ 2
4,096 ´ 1
256 ´ 16
(1),
512 ´ 8
(2)
D
ENA
Q
Altera Corporation
To MultiTrack
Interconnect
July 2005

Related parts for EP1S25F1020C5